參數(shù)資料
型號: M37272MA-309SP
廠商: Mitsubishi Electric Corporation
英文描述: Silver Mica Capacitor; Capacitance:10pF; Capacitance Tolerance: 0.5pF; Series:CM04; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3.6mm; Leaded Process Compatible:No RoHS Compliant: No
中文描述: 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù): 40/131頁
文件大?。?/td> 1297K
代理商: M37272MA-309SP
40
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6H/M8H/MAH/MFH
XXXSP/FP
M37272E8SP/FP, M37272EFSP/FP
MITSUBISHI MICROCOMPUTERS
Rev 1.0
Fig. 8.6.12 Address Data Communication Format
S
S
l
a
v
e
e
r
a
d
d
r
e
s
s
A
D
a
t
a
A
D
a
t
a
A
/
A
P
R
0
r
t
/
W
7
b
t
r
i
a
t
s
n
1
a
d
t
t
o
a
8
t
o
b
a
i
t
s
s
1 to 8 bits
e
c
e
i
v
S
S
l
a
v
e
e
r
a
d
d
r
e
s
s
A
D
a
t
a
A
D
a
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a
A
P
7
b
r
e
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t
c
s
e
1
c
e
i
1
f
t
o
o
8
a
b
i
s
t
s
l
1 to 8 bits
a
n
s
m
(1
)
A
m
a
s
t
-
s
m
i
t
t
e
r
a
n
s
m
i
t
s
l
a
v
e
-
r
e
r
S
Slave address
1st 7 bits
b
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
A
A
D
a
t
a
7
i
t
s
0
8
b
i
t
s
1 to 8 bits
(2
)
A
m
a
s
t
-
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v
e
r
r
e
v
e
s
d
a
t
a
r
m
a
v
e
-
t
r
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t
t
e
r
Slave address
2nd byte
A
D
a
t
a
A/A
P
1 to 8 bits
S
Slave address
1st 7 bits
A
A
7 bits
e
r
-
r
0
c
e
8 bits
a
s
7 bits
-
b
i
t
Slave address
2nd byte
D
a
t
a
1 to 8 bits
S
r
Slave address
1st 7 bits
A
D
a
t
a
A
P
1 to 8 bits
1
(4
)
A
m
a
s
t
e
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t
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a
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m
i
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t
e
r
w
i
t
h
a
1
0
a
d
d
r
e
s
s
S : S
A : A
S
r : R
T
C
e
A
K
s
R
t
a
T
i
r
t
c
o
n
d
i
t
i
o
n
P
R
/
:
W
S
T
:
O
R
P
e
c
d
o
/
n
W
d
r
i
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t
t
i
e
o
n
b
b
t
a
i
t
c
o
n
d
i
t
i
o
n
From master to slave
F
o
m
s
l
a
v
e
r
t
o
m
a
s
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r
R
/
W
R
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R
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R
/
W
8.6.12 Precautions when using multi-master
I
2
C-BUS interface
(1) Read-modify-write instruction
The precautions when the raead-modify-write instruction such as SEB,
CLB etc. is executed for each register of the multi-master I
2
C-BUS
interface are described below.
I
2
C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become a value not intended.
I
2
C address register (S0D)
When the read-modify-write instruction is executed for this register
at detecting the STOP condition, data may become a value not
intended. It is because hardware changes the read/write bit (RBW)
at the above timing.
I
2
C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
I
2
C control register (S1D)
When the read-modify-write instruction is executed for this register
at detecting the START condition or at completing the byte transfer,
data may become a value not intended. Because hardware changes
the bit counter (BC0–BC2) at the above timing.
I
2
C clock control register (S2)
The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure us-
ing multi-master
Procedure example (The necessary conditions of the generating
procedure are described as the following
to
).
LDA
SEI
BBS 5,S1,BUSBUSY
BUSFREE:
STA S0
LDM #$F0, S1
CLI
(Taking out of slave address value)
(Interrupt disabled)
(BB flag confirming and branch process)
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
BUSBUSY:
CLI
(Interrupt enabled)
Use “STA,” “STX” or “STY” of the zero page addressing instruction
for writing the slave address value to the I
2
C data shift register.
Use “LDM” instruction for setting trigger of START condition gener-
ating.
Write the slave address value of above
and set trigger of START
condition generating of above
continuously shown the above
procedure example.
Disable interrupts during the following three process steps:
BB flag confirming
Writing of slave address value
Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
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