參數(shù)資料
型號(hào)： M37225ECSP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
中文描述： 單芯片8位CMOS微機(jī)電壓合成與屏幕顯示控制器
文件頁數(shù)： 44/133頁
文件大?。?/td> 1610K
代理商： M37225ECSP
44
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
M37225M6–XXXSP, M37225M8–XXXSP
M37225ECSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
8.7 PWM OUTPUT FUNCTION
This microcomputer is equipped with two 14-bit PWMs (DA1, DA2)
and six 8-bit PWMs (PWM0–PWM5). DA1 and DA2 have a 14-bit
resolution with the minimum resolution bit width of 0.25
μ
s and a
repeat period of 4096
μ
s (for f(X
IN
) = 8 MHz). PWM0–PWM5 have
the same circuit structure and an 8-bit resolution with minimum reso-
lution bit width of 4
μ
s and repeat period of 1024
μ
s (for f(X
IN
) = 8
MHz).
Figure 8.7.1 shows the PWM block diagram. The PWM timing gen-
erating circuit applies individual control signals to DA1, DA2 and
PWM0–PWM5 using f(X
IN
) divided by 2 as a reference signal.
8.7.1 Data Setting
When outputting DA1, first set the high-order 8 bits to the DA1-H
register (address 00CE
16
), then the low-order 6 bits to the DA1-L
register (address 00CF
16
). When outputting DA1, first set the high-
order 8 bits to the DA2-H register (address 024E
16
), then the low-
order 6 bits to the DA2-L register (address 024F
16
). When outputting
PWM0–PWM5, set 8-bit output data to the PWMi register (i means 0
to 5; addresses 00D0
16
to 00D4
16
, 00F6
16
).
8.7.2 Transferring Data from Registers to PWM
Circuit
Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is
executed at writing data to the register.
The signal output from the 8-bit PWM output pin corresponds to the
contents of this register.
Also, data transfer from the DA1 register (addresses 00CE
16
and
00CF
16
) to the 14-bit PWM circuit is executed at writing data to the
DA1-L register (address 00CF
16
). Reading from the DA1-H register
(address 00CE
16
) means reading this transferred data. Data trans-
fer from the DA2 register (addresses 024E
16
and 024F
16
) to the 14-
bit PWM circuit is executed at writing data to the DA2-L register (ad-
dress 024F
16
). Reading from the DA2-H register (address 024E
16
)
means reading this transferred data. Accordingly, it is possible to
confirm the data being output from the DAi (i = 1, 2) output pin by
reading the DAi (i = 1, 2) register.
8.7.3 Operating of 8-bit PWM
The following explains PWM operation.
First, set the bit 0 of PWM output control register 1 (address 00D5
16
)
to “0” (at reset, bit 0 is already set to “0” automatically), so that the
PWM count source is supplied.
PWM0–PWM5 are also used as pins P0
0
–P0
5
, respectively. For
PWM0–PWM5, set the corresponding bits of the ports P0 direction
register to “1” (output mode). And select each output polarity by bit 3
of PWM output control register 2 (address 00D6
16
). Then, set bits 2
to 7 of PWM output control register 1 to “1” (PWM output).
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 8.7.2 shows the 8-bit PWM timing. One cycle (T) is com-
posed of 256 (2
8
) segments. The 8 kinds of pulses, relative to the
weight of each bit (bits 0 to 7), are output inside the circuit during 1
cycle. Refer to Figure 8.7.2 (a). The 8-bit PWM outputs waveform
which is the logical sum (OR) of pulses corresponding to the con-
tents of bits 0 to 7 of the 8-bit PWM register. Several examples are
shown in Figure 8.7.2 (b). 256 kinds of output (HIGH area: 0/256 to
255/256) are selected by changing the contents of the PWM register.
A length of entirely HIGH output cannot be output, i.e. 256/256.
8.7.4 Operating of 14-bit PWM
For DA1, as with 8-bit PWM, set the bit 0 of PWM output control
register 1 (address 00D5
16
) to “0” (at reset, bit 0 is already set to “0”
automatically), so that the PWM count source is supplied. Next, se-
lect the output polarity by bit 2 of PWM output control register 2 (ad-
dress 00D6
16
). Then, the 14-bit PWM outputs from the DA1 output
pin by setting bit 1 of PWM output control register 1 to “0” (at reset,
this bit already set to “0” automatically) to select the DA1 output.
For DA2 as with DA1, set the bit 0 of PWM output control register 1
(address 00D5
16
) to “0” (at reset, bit 0 is already set to “0” automati-
cally), so that PWM count source is supplied. Next, select the output
polarity by bit 4 of PWM output control register 2 (address 00D6
16
).
Then, the 14-bit PWM outputs from the DA2 output pin by setting
bit 5 of PWM output control register 1 to “0” (at reset, this bit already
set to “0” automatically) to select the DA2 output.
The output example of the 14-bit PWM is shown in Figure 8.7.3.
The 14-bit PWM divides the data of the DAi latch (i = 1, 2) into the
low-order 6 bits and the high-order 8 bits.
The fundamental waveform is determined with the high-order 8-bit
data “D
H
.” A HIGH area with a length t
D
H
(HIGH area of funda-
mental waveform) is output every short area of “t” = 256
τ
=
64
μ
s (
τ
is the minimum resolution bit width of 250 ns). The HIGH
level area increase interval (t
m
) is determined with the low-order 6-bit
data “D
L
.” The HIGH are of smaller intervals “t
m
” shown in Table 5 is
longer by t than that of other smaller intervals in PWM repeat period
“T” = 64t. Thus, a rectangular waveform with the different HIGH width
is output from the DAi pins (i = 1, 2). Accordingly, the PWM output
changes by
τ
unit pulse width by changing the contents of the DAi-H
and DAi-L registers (i = 1, 2). A length of entirely HIGH cannot be
output, i. e. 256/256.
8.7.5 Output after Reset
At reset, the output of ports P0
0
–P0
5
and P1
7
are in the high-imped-
ance state, and the contents of the PWM register and the PWM
circuit are undefined. Note that after reset, the PWM output is unde-
fined until setting the PWM register.
LSB
Table 8.7.1 Relation Between the Low-order 6-bit Data and High-
level Area Increase Interval
Area Longer by
τ
than That of Other t
m
(m = 0 to 63)
Nothing
m = 32
m = 16, 48
m = 8, 24, 40, 56
m = 4, 12, 20, 28, 36, 44, 52, 60
m =
2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m = 1, 3, 5, 7,................................. 57, 59, 61, 63
Low-order 6 bits of Data
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
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