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| 型號(hào)： | M37221M6 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits Microcomputer(8位單片機(jī)) |
| 中文描述： | 單芯片8位單片機(jī)（8位單片機(jī)） |
| 文件頁(yè)數(shù)： | 25/61頁(yè) |
| 文件大小： | 1386K |
| 代理商： | M37221M6 |
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MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
25
When the first-byte address data matches the slave address, the
AAS bit of the I
2
C status register (address 00D9
16
) is set to “1.” After
the second-byte address data is stored into the I
2
C data shift register
(address 00D7
16
), make an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd byte matches the slave address, set the RBW bit of
the I
2
C address register (address 00D8
16
) to “1” by software. This
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I
2
C address register (address 00D8
16
). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 22, (3) and (4).
(10) Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
Set a slave address in the high-order 7 bits of the I
2
C address
register (address 00D8
16
) and “0” in the RBW bit.
Set the ACK return mode and SCL = 100 kHz by setting “85
16
” in
the I
2
C clock control register (address 00DB
16
).
Set “10
16
” in the I
2
C status register (address 00D9
16
) and hold
the SCL at the “H” level.
Set a communication enable status by setting “48
16
” in the I
2
C
control register (address 00DA
16
).
Set the address data of the destination of transmission in the high-
order 7 bits of the I
2
C data shift register (address 00D7
16
) and set
“0” in the least significant bit.
Set “F0
16
” in the I
2
C status register (address 00D9
16
) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
Set transmit data in the I
2
C data shift register (address 00D7
16
).
At this time, an SCL and an ACK clock automatically occurs.
When transmitting control data of more than 1 byte, repeat step
.
Set “D0
16
” in the I
2
C status register (address 00D9
16
). After this,
if ACK is not returned or transmission ends, a STOP condition
occurs.
(11) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode and using
the addressing format is shown below.
Set a slave address in the high-order 7 bits of the I
2
C address
register (address 00D8
16
) and “0” in the RBW bit.
Set the no ACK clock mode and SCL = 400 kHz by setting “25
16
”
in the I
2
C clock control register (address 00DB
16
).
Set “10
16
” in the I
2
C status register (address 00D9
16
) and hold
the SCL at the “H” level.
Set a communication enable status by setting “48
16
” in the I
2
C
control register (address 00DA
16
).
When a START condition is received, an address comparison is
made.
When all transmitted addresses are “0” (general call)
AD0 of the I
2
C status register (address 00D9
16
) is set to “1” and
an interrupt request signal occurs.
When the transmitted addresses match the address set in
AAS of the I
2
C status register (address 00D9
16
) is set to “1” and
an interrupt request signal occurs.
In the cases other than the above
AD0 and AAS of the I
2
C status register (address 00D9
16
) are
set to “0” and no interrupt request signal occurs.
Set dummy data in the I
2
C data shift register (address 00D7
16
).
When receiving control data of more than 1 byte, repeat step
.
When a STOP condition is detected, the communication ends.
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