
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37151M6/M8/MA/MC/MF-XXXFP, M37151EFFP
MITSUBISHI MICROCOMPUTERS
40
Rev 1.0
Fig. 8.6.13 Address Data Communication Format
8.6.12 Precautions when using multi-master
I
2
C-BUS interface
(1) Read-modify-write instruction
Precautions for executing the read-modify-write instructions, such
as SEB and CLB, is for each register of the multi-master I
2
C-BUS
interface are described below.
I
2
C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become an arbitrary value.
I
2
C address register (S0D)
When the read-modify-write instruction is executed for this register
at detection of the STOP condition, data may become an arbitrary
value because hardware changes the read/write bit (RBW) at the
above timing.
I
2
C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
I
2
C control register (S1D)
When the read-modify-write instruction is executed for this register
at detection of the START condition or at completion of the byte
transfer, data may become an arbitrary value because hardware
changes the bit counter (BC0–BC2) at the above timing.
I
2
C clock control register (S2)
The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure us-
ing multi-master
Procedure example (The necessary conditions for the procedure
are described in
to
below).
—
LDA
SEI
BBS 5,S1,BUSBUSY
(Take at slave address value)
(Interrupt disabled)
(BB flag confirmation and branch
process)
BUSFREE:
STA S0
LDM #$F0, S1
CLI
(Write slave address value)
(Trigger START condition generation)
(Interrupt enabled)
BUSBUSY:
CLI
(Interrupt enabled)
Use “STA,” “STX” or “STY” of the zero page addressing instruc-
tion for writing the slave address value to the I
2
C data shift register.
Use “LDM” instruction for setting trigger of START condition gen-
eration.
Write the slave address value of
and set trigger of START con-
dition generation as in
continuously, as shown in the procedure
example.
Disable interrupts during the following three process steps:
BB flag confirmation
Write slave address value
Trigger of START condition generation
When the condition of the BB flag is bus busy, enable interrupts
immediately.
S
S
l
a
v
e
e
r
a
d
d
r
e
s
s
A
D
a
t
a
A
Data
A/A
P
R
“0
r
t
/
W
7
b
t
r
i
a
t
s
n
”
1
a
d
t
t
o
a
8
t
o
b
a
i
t
s
s
1 to 8 bits
e
c
e
i
v
S
S
l
a
v
e
e
r
a
d
d
r
e
s
s
A
D
a
t
a
A
Data
A
P
7
b
r
e
i
t
c
s
e
“1
c
e
”
i
1
f
t
o
o
8
a
b
i
s
t
s
l
1 to 8 bits
a
n
s
m
(1
)
A
m
a
s
t
-
s
m
i
t
t
e
r
a
n
s
m
i
t
s
l
a
v
e
-
r
e
r
S
Slave address
1st 7 bits
A
A
D
a
t
a
7 bits
e
r
-
t
“0”
t
r
8 bits
o
a
1 to 8 bits
r
w
i
t
h
(2
)
A
m
a
s
t
-
i
v
e
r
r
e
v
e
s
d
a
t
a
r
m
a
v
e
-
t
r
i
t
t
e
r
Slave address
2nd byte
A
D
a
t
a
A
/
A
P
1 to 8 bits
d
d
r
e
s
S
S
1
l
a
t
v
7
e
b
a
i
d
t
s
d
r
e
s
s
s
A
A
7 bits
e
r
-
r
“0”
c
e
8 bits
a
s
7 bits
-
b
i
t
(3
)
A
m
a
s
t
r
a
n
s
m
i
t
t
e
r
a
n
s
m
i
t
s
d
a
t
a
t
s
l
a
v
e
-
r
e
c
e
i
v
e
a
1
0
-
b
i
t
a
s
S
2
l
a
d
v
e
b
y
a
t
d
e
d
r
e
s
s
n
D
a
t
a
1 to 8 bits
Sr
S
1
l
a
t
v
7
e
b
a
i
d
t
s
d
r
e
s
s
s
A
D
a
t
a
A
P
1 to 8 bits
“1”
(4
)
A
m
a
s
t
e
c
e
i
v
e
r
r
e
i
v
e
s
d
a
t
a
f
r
o
m
l
a
v
e
-
t
r
a
n
s
m
i
t
t
e
r
w
i
t
h
a
1
0
a
d
d
r
e
s
s
S : S
A : A
S
r : R
T
C
e
A
K
s
R
t
a
T
i
r
t
c
o
n
d
i
t
i
o
n
P
R
/
:
W
S
T
:
O
R
P
e
c
d
o
/
n
W
d
r
i
i
t
t
i
e
o
n
b
b
t
a
i
t
c
o
n
d
i
t
i
o
n
From master to slave
F
o
m
s
l
a
v
e
r
t
o
m
a
s
t
e
r
R
/
W
R
/
W
R
/
W
R
/
W