參數(shù)資料
型號: M34583MD-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù): 71/153頁
文件大?。?/td> 947K
代理商: M34583MD-XXXFP
Rev.3.00
Aug 06, 2004
page 24 of 151
REJ03B0009-0300Z
4583 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 7 External interrupt activated conditions
Name
External 0 interrupt
External 1 interrupt
Input pin
P30/INT0
P31/INT1
Activated condition
When the next waveform is input to P30/INT0 pin
Falling waveform (“H”
→“L”)
Rising waveform (“L”
→“H”)
Both rising and falling waveforms
When the next waveform is input to P31/INT1 pin
Falling waveform (“H”
→“L”)
Rising waveform (“L”
→“H”)
Both rising and falling waveforms
Valid waveform
selection bit
I11
I12
I21
I22
Fig. 17 External interrupt circuit structure
EXTERNAL INTERRUPTS
The 4583 Group has the external 0 interrupt and external 1 inter-
rupt.
An external interrupt request occurs when a valid waveform is input
to an interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
registers I1 and I2.
Rising
Falling
One-sided edge
detection circuit
Key-on wakeup
External 1
interrupt
Timer 3 count start
synchronous circuit
Level detection circuit
Edge detection circuit
Skip decision
(SNZI1 instruction)
Both edges
detection circuit
0
1
I22
0
1
EXF1
I21
P31/INT1
K22
I23
0
1
K23
Rising
0
1
Falling
I12
One-sided edge
detection circuit
Key-on wakeup
0
1
EXF0
External 0
interrupt
I11
P30/INT0
K20
Timer 1 count start
synchronous circuit
I13
(Note 1)
Level detection circuit
Edge detection circuit
0
1
K21
Skip decision
(SNZI0 instruction)
Both edges
detection circuit
This symbol represents a parasitic diode on the port.
Notes 1:
(Note 2)
(Note 3)
(Note 1)
(Note 2)
(Note 3)
2: I12 (I22) = 0: “L” level detected
I12 (I22) = 1: “H” level detected
3: I12 (I22) = 0: Falling edge detected
I12 (I22) = 1: Rising edge detected
Period measurement circuit input
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