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參數(shù)資料
| 型號(hào)： | M3455AGC-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 |
| 文件頁(yè)數(shù)： | 71/150頁(yè) |
| 文件大?。?/td> | 1818K |
| 代理商： | M3455AGC-XXXFP |
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Rev.1.02
Nov 26, 2008
Page 25 of 146
REJ03B0224-0102
455A Group
(6) Interrupt control registers
Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are
assigned to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can
be used to transfer the contents of register V1 to register A.
Interrupt control register V2
The timer 3 interrupt enable bit are assigned to register V2. Set
the contents of this register through register A with the TV2A
instruction. The TAV2 instruction can be used to transfer the
contents of register V2 to register A.
Note 1.“R” represents read enabled, and “W” represents write enabled.
(7) Interrupt sequence
Interrupts occur only when the respective INTE flag, interrupt
enable bits (V10, V12, V13, V30), and interrupt request flag are
set to “1.” The interrupt occurs two or three cycles after the cycle
where all the above three conditions are satisfied.
The interrupt occurs after three machine cycles if instructions
other than one-cycle instruction are executed when the
conditions are satisfied (Refer to Figure 27).
Table 13 Interrupt control registers
Interrupt control register V1
at reset : 00002
at power down : 00002
R/W
TAV1/TV1A
V13
Timer 2 interrupt enable bit
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
V12
Timer 1 interrupt enable bit
0
Interrupt disabled (SNZT1 instruction is valid)
1
Interrupt enabled (SNZT1 instruction is invalid)
V11
Not used
0
This bit has no function, but read/write is enabled.
1
V10
External 0 interrupt enable bit
0
Interrupt disabled (SNZ0 instruction is valid)
1
Interrupt enabled (SNZ0 instruction is invalid)
Interrupt control register V2
at reset : 00002
at power down : 00002
R/W
TAV2/TV2A
V23
Not used
0
This bit has no function, but read/write is enabled.
1
V22
Not used
0
This bit has no function, but read/write is enabled.
1
V21
Not used
0
This bit has no function, but read/write is enabled.
1
V20
Timer 3 interrupt enable bit
0
Interrupt disabled (SNZT3 instruction is valid)
1
Interrupt enabled (SNZT3 instruction is invalid)
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| M3455AG8-XXXFP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP52 |
| M34570MD-XXXFP | 4-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO36 |
| M34570E8FP | 4-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO36 |
| M34583EDFP | 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP32 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M3455-SL001 | 制造商:Alpha Wire 功能描述: |
| M3455-SL002 | 制造商:Alpha Wire 功能描述: |
| M3455-SL005 | 制造商:Alpha Wire 功能描述: |
| M3455-SL199 | 制造商:Alpha Wire 功能描述: |
| M3455-SLATE-100 | 制造商:Alpha Wire 功能描述: |
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