參數(shù)資料
型號: M34518M4-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù): 128/157頁
文件大小: 1783K
代理商: M34518M4-XXXFP
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 5
Interrupts (INTs)
5 – 11
5.2.10
Interrupt Request Register 1 (IRQ1)
Address: 0F019H
Access: R/W
Access size: 8 bits
Initial value: 00H
7
6
5
4
3
2
1
0
IRQ1
QP03
QP02
QP01
QP00
R/W
Initial value
0
IRQ1 is a special function register (SFR) to request an interrupt for each interrupt source.
Each IRQ1 request flag is set to “1” regardless of the IE1 and MIE values when an interrupt is generated.
In this case,
an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE1) is set to “1” and the
master interrupt enable flag (MIE) is set to “1”.
By setting the IRQ1 request flag to “1” by software, an interrupt can be generated.
The corresponding flag of IRQ1 is set to “0” by hardware when the interrupt request is accepted by the CPU.
[Description of Bits]
QP00 (bit 0)
QP00 is the request flag for the input port P00 pin interrupt (P00INT).
QP00
Description
0
No request (initial value)
1
Request
QP01 (bit 1)
QP01 is the request flag for the input port P01 pin interrupt (P01INT).
QP01
Description
0
No request (initial value)
1
Request
QP02 (bit 2)
QP02 is the request flag for the input port P02 pin interrupt (P02INT).
QP02
Description
0
No request (initial value)
1
Request
QP03 (bit 3)
QP03 is the request flag for the input port P03 pin interrupt (P03INT).
QP03
Description
0
No request (initial value)
1
Request
Note:
When an interrupt is generated by the write instruction to the interrupt request register (IRQ1) or to the interrupt enable
register (IE1), the interrupt shift cycle starts after the next 1 instruction is executed.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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