參數(shù)資料
型號(hào): M34506M2-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, MICROCONTROLLER, PDSO20
封裝: 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20
文件頁(yè)數(shù): 8/114頁(yè)
文件大?。?/td> 836K
代理商: M34506M2-XXXFP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
4
4-16
EIT
32180 Group User’s Manual (Rev.1.0)
4.9 Interrupt Processing
16-bit instruction
Order in which instructions are executed
32-bit instruction
Address 1000
Address 1002
Address 1004
Address 1000
Interrupt may
be accepted
×
Interrupt cannot
be accepted
16-bit instruction
Interrupt may
be accepted
Interrupt may
be accepted
Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM
SM
BIE
IE
BC
C
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM
0
IE
0
C
0
(3) Saving the PC
The address of the next instruction (always on word boundary) following one in which the interrupt was
detected is stored in the BPC register. If the interrupt was detected in a branch instruction, then the next
instruction is one that exists at the jump address.
(4) Branching to the EIT vector entry
The CPU branches to the address H’0000 0010 in the user space. This is the last operation performed in
hardware preprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the address H’0000 0010 of the EIT vector
entry to jump to the start address of the user-created handler.
The system break interrupt can only be used when the system has some fatal event already existing in it
when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the
SBI handler, control will not return to the program that was being executed when the system break interrupt
occurred.
相關(guān)PDF資料
PDF描述
M34507E4FP 4-BIT, OTPROM, MICROCONTROLLER, PDSO24
M34507M2-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO24
M34507M4-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO24
M34507M2-XXXFP 4-BIT, MROM, MICROCONTROLLER, PDSO24
M34509G4FP 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO24
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M34506M4 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34506M4-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
M34507E4FP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34507M2-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
M34507M4-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER