
Rev.1.00
Aug 06, 2008
page 19 of 64
REJ03B0251-0100
4286 Group
Fig. 21 Internal state at reset
VOLTAGE DROP DETECTION CIRCUIT
System reset is performed when the supply voltage goes the
reset occurrence voltage or less.
When the supply voltage goes reset release voltage or more,
the oscillation circuit goes to be in the operating enabled state
and system reset is released.
The reset occurrence voltage value is selectable by the CLVD
instruction execution.
Refer to the electrical characteristics for reset occurrence value
and reset release voltage value.
The voltage drop detection circuit is stopped and power
dissipation is reduced in the RAM back-up mode with the
initialized CPU stopped.
Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
As the actual operating minimum voltage is lower than the
reset generation voltage, the MCU will operate correctly unless
oscillation stops before the supply voltage reaches the reset
generation voltage during CPU operation.
Fig. 22 Voltage drop detection circuit operation waveform
Program counter (PC) ..............................................................
Address 0 in page 0 is set to program counter.
Power down flag (P) .................................................................
Timer 1 underflow flag (T1F) ...................................................
Timer 2 underflow flag (T2F) ...................................................
Timer control register V1 ..........................................................
Timer control register V2 ..........................................................
Port CARR output flag (CAR) ..................................................
Pull-down control register PU0 ................................................
Pull-down control register PU1 ................................................
Pull-down control register PU2 ................................................
Logic operation selection register LO ......................................
Most significant ROM code reference enable flag (URS)
Carry flag (CY) .........................................................................
Register A .................................................................................
Register B .................................................................................
Register X .................................................................................
Register Y .................................................................................
Stack pointer (SP) ....................................................................
000
00
0
000
0
000
0
000
0
000
0
00
0
111
1
111
1
11
Fig. 23 VDD and VDET
VDD
Recommended operating
condition min.value
Even if the voltage re-goes up to
the recommended operating voltage,
MCU may not operate correctly.
Oscillation is stopped
incorrectly.
VDET
VDD
Recommended
operating condition
min.value
VDET
→ Normal operation
Reset
“” represents undefined.
When designing a system, test the operation thoroughly by
confirming the oscillation stop voltage and frequency of the
oscillator.
(Note)
Internal reset signal
CLVD instruction
VDD
Reset occurrence/release voltage TYP = 1.7V
Reset occurrence voltage TYP = 1.5V
(Note)
Note: Microcomputer starts operation after f(XIN) is counted to 16384 times.