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參數(shù)資料
| 型號： | M34286G2-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20 |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 516K |
| 代理商： | M34286G2-XXXGP |
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Rev.1.00
Aug 06, 2008
page 18 of 64
REJ03B0251-0100
4286 Group
Fig. 19 Reset release timing
RESET FUNCTION
The 4286 Group has the power-on reset circuit, though it does
not have RESET pin. System reset is performed automatically
at power-on, and software starts program from address 0 in page
0.
In order to make the built-in power-on reset circuit operate
efficiently, set the voltage rising time until VDD= 0 to 2.2 V is
obtained at power-on 1ms or less (Ta = –20 °C to 85 °C).
Fig. 20 Power-on reset operation
f(XIN)
Internal reset signal
f(XIN) 16384 pulses
Software operation starts
(address 0 in page 0)
“H”
“L”
VDD
Internal reset signal
Power-on reset circuit
Voltage drop detection circuit
Watchdog timer output
Power-on reset circuit
output voltage
Reset state
Internal reset signal
Reset released
Power-on
Note on Power-on reset
Under the following condition, the system reset occurs by the
built-in the power-on reset circuit of this product;
-
when the supply voltage (VDD) rises from 0 V to 2.2 V, within
1 ms (Ta = –20 °C to 85 °C).
Also, note that system reset does not occur under the
following conditions;
-
when the supply voltage (VDD) rises from the voltage higher
than 0V, or
-
when it takes more than 1 ms for the supply voltage (VDD)
to rise from 0 V to 2.2 V (Ta = –20 °C to 85 °C).
(1) Internal state at reset
Table 6 shows port state at reset, and Figure 21 shows internal
state at reset (they are retained after system is released from
reset).
The contents of timers, registers, flags and RAM except shown
in Figure 21 are undefined, so set the initial value to them.
Table 6 Port state at reset
Name
D0–D7
G0–G3
E0, E1
CARR
State at reset
High impedance state (Pull-down transistor OFF)
“L” output
Note: The contents of all output latch is initialized to “0.”
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