
MITSUBISHI
ELECTRIC
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
63
MITSUBISHI MICROCOMPUTERS
4282 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Fig. 31 Timing at program verifying
and pull the PGM pin to
“
L.
”
When this is done, the program
data is programmed to the specified address.
(4) Program
Input command code 25
16
in the first transfer. Proceed and
input the low-order 8 bits and high-order 8 bits of the address
and the low-order 8 bits and high-order 8 bits of program data,
Fig. 30 Timing at programming
(5) Program verify
Input command code 35
16
in the first transfer. Proceed and
input the low-order 8 bits and high-order 8 bits of the address
and the low-order 8 bits and high-order 8 bits of program data,
and pull the PGM pin to
“
L.
”
When this is done, the program
data is programmed to the specified address. Then, when the
PGM pin is pulled to
“
L
”
again after it is released back to
“
H,
”
the address programmed with the program command is read
and verified and stored into the internal data latch. When the
PGM pin is released back to
“
H
”
and serial clock is input to the
SCLK pin, the verify data that has been stored into the data
latch is serially output from the SDA pin.
Note: When outputting the verify data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is
placed in the high-impedance state during the th
(C
–
E)
period after the last rising edge of the serial clock (at the 16th bit).
1 0 1 0 0 1 0 0
Commanf code input (25
16
)Program address input (L) Program address input (H)
A0
A7
SCLK
SDA
PGM
Program
t
CH
D0
D7
Program data input (L)
t
CP
t
WP
t
CH
D8
Program data input (H)
t
CH
0 0 0 0 0 0 0
t
CH
A8A9
0 0 0 0 0
A10
1 0 1 0 1 1 0 0
A0
A7
Command code input (35
16
)
Program address input (L)
Program address input (H)
SCLK
SDA
PGM
t
CH
D0
D7
Program data input (L)
t
CP
t
WP
t
CH
D8
Program data input (H)
t
CH
0 0 0 0 0 0 0
t
CH
A8A9
0 0 0 0 0
Program
t
CR
t
RC
SCLK
SDA
PGM
Verify
t
WR
D0
D7
Verify data output (L)
D8
Verify data output (H)
t
CH
0 0 0 0 0 0 0
A10