11
11-22
A-D Converter
32176 Group User’s Manual (Rev.1.01)
11.2 A-D Converter Related Registers
11.2.5 A-D Conversion Speed Control Register
A-D0 Conversion Speed Control Register (AD0CVSCR)
<Address: H’0080 0087>
<Upon exiting reset: H’00>
b
Bit Name
Function
R
W
8–14
No function assigned. Fix to "0".
00
15
ADCVSD (Note 1)
0: Slow mode
R
W
A-D conversion speed control bit
1: Fast mode
Note 1: The A-D conversion speed is determined by a combination of ADCVSD bit and A-D Single Mode Register 1’s relevant bit
during single mode, or a combination of ADCVSD bit and A-D Scan Mode Register 1’s relevant bit during scan mode.
The A-D Conversion Speed Control Register controls the A-D conversion speed during single and scan modes
of the A-D Converter. The A-D conversion speed is determined in combination with A-D Single Mode Register
1's conversion speed select bit (Double/Normal).
b8
9
10
11121314
b15
ADCVSD
0000000
0
