20
20-11
32170/32174 Group User's Manual (Rev. 2.1)
POWER-ON/POWER-SHUTDOWN SEQUENCE
20.3 Power-Shutdown Sequence
(a)
(b)
VCCE
AVCC0,
AVCC1
VREF0,
VREF1
P72 / HREQ
RESET
VDD
VCCI
FVCC
OSC-VCC
3.3V
(c)
0V
(d)
2.0V
(a):
__________
Pull the HREQ pin input low to halt the CPU at end of bus cycle. Or disable RAM access in
software. The M32R/ECU allows P72 to be used as HREQ irrespective of its operation
mode.
(b):
____________
With the CPU halted, pull the RESET pin input low. Or while RAM access is disabled, pull
____________
the RESET pin input low.
(c):
____________
Turn off the power supply after the RESET pin goes low.
(d): Reduce the VDD voltage from 3.3 V to 2.0 V as necessary.
Note: Power-shutdown requirements
VDD
VCCI
FVCC
OSC-VCC
VCCI
Figure 20.3.4 Power-Shutdown Sequence When Using RAM Backup(when VCC=3.3V)
