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參數(shù)資料
| 型號(hào)： | M32000D3FP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 66.6 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 5/155頁(yè) |
| 文件大?。?/td> | 1340K |
| 代理商： | M32000D3FP |
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7-4
M32000D3FP User's Manual
MASTER/SLAVE MODE
7.2 Slave mode operation
7.2.2 Bus control signals in slave mode
When the M32000D3FP is set to slave mode, pins are in the high-impedance state while the reset signal
___
is being input. After a reset, the pins are returned to normal operation even when M/S = "L". To ensure
__________
pins stay in the high-impedance state after a reset, keep HREQ to an "L" level until the reset state is
released.
Table 7.2.1 Pin condition in slave mode
pin name
at reset
after a reset
____
___
A8 - A30, SID, BCH, BCL, high-impedance
_____
high-impedance at hold state (HACK = "L")
__
___
______
ST, R/W, BS, BURST
normal operation in other than hold state
D0 - D15
high-impedance
_____
high-impedance at hold state (HACK = "L") (see note 1)
normal operation in other than hold state
___
DC
high-impedance
_____
high-impedance at hold state (HACK = "L") (see note 2)
normal operation in other than hold state
other pins
undefined
normal operation
___
__
Notes 1: Outputs when the internal DRAM is read by an external source (CS = "L", R/W = "H")
___
2: Outputs when the internal DRAM is accessed by an external source (CS = "L")
7.2.3 Operation in slave mode
In a multi-CPU configuration with a master M32000D3FP and slave M32000D3FP, and when the master
M32000D3FP has the system bus right, the slave M32000D3FP can only access its own internal DRAM.
The slave M32000D3FP can access the external bus when it has been given the system bus access right
after bus arbitration between the master and slave has taken place.
The slave M32000D3FP operates by communicating with the master M32000D3FP, using the two
______
programmable I/O ports and the INT pin. When a data transaction is necessary between the master and
__________
slave, they access one another’s internal DRAM using the HREQ and HACK signals to arbitrate system
bus rights.
7.2.4 Returning from standby mode in slave mode
______
_________
When the M32000D3FP is set to slave mode, on return from standby mode, either after a RST or WKUP
input, it does not execute an instruction fetch to the reset vector entry (action on return from standby is
_____
equivalent to a reset). Instead it waits for an "L" level input to INT or SBI and then starts operation by an
instruction fetch to the corresponding interrupt vector entry.
7.2.5 Ensuring data coherency
In a multi-CPU configuration, when the master and slave M32000D3FP use the same data, data coherency
should be ensured. Basically, the two CPUs carry out a handshake using their programmable I/O ports and
external interrupt functions.
The M32000D3FP has instructions to access the common resources such as the internal DRAM or external
memory exclusive from other external bus masters. This is effective in ensuring data coherency.
LOCK: The LOCK bit is set in loading.
UNLOCK: The LOCK bit is cleared in storing.
When the LOCK bit is "1", hold requests and the internal DRAM access requests from an external bus
master are not accepted. For details, refer to 5.5.2 "Memory controller control register" and "M32R family
software manual".
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