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參數(shù)資料
| 型號： | M30882FJTGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 31/60頁 |
| 文件大?。?/td> | 458K |
| 代理商： | M30882FJTGP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3826 Group
38
D-A Converter
The 3826 group has an on-chip D-A converter with 8-bit resolution
and 2 channels (DAi (i=1, 2)). After the DTMF/DA1 selection bit or
CTCSS/DA2 selection bit is set to “0”, the D-A converter is per-
formed by setting the value in the D-A conversion register. The
result of D-A converter is output from DAi pin by setting the DTMF/
DA1 output enable bit or CTCSS/DA2 output enable bit to “1”.
When using the D-A converter, the corresponding port direction
register bit (P56/DA1, P57/DA2) should be set to “0” (input status)
and the pull-up resistor should be in the OFF state.
The output analog voltage V is determined by the value n (base
10) in the D-A conversion register as follows:
V=VREF n/256 (n=0 to 255)
Where VREF is the reference voltage.
At reset, the D-A conversion registers are cleared to “0016”, the
DTMF/DA1 output enable bit or CTCSS/DA2 output enable bit are
cleared to “0”, and DAi pin goes to high impedance state. The DA
output is not buffered, so connect an external buffer when driving
a low-impedance load.
s Note on applied voltage to VREF pin
When the P56/DA1 pin and P57/DA2 pin are used as I/O ports, be
sure to apply Vcc level to VREF pin.
When these pins are used as D-A conversion output pins, the Vcc
level is recommended for the applied voltage to VREF pin.
When the voltage below Vcc level is applied, the D-A conversion
accuracy may be worse.
Fig. 38 Structure of D-A control register
Fig. 39 Block diagram of D-A converter
DTMF/DA1 output enable bit
0 : Disabled
1 : Enabled
CTCSS/DA2 output enable bit
0 : Disabled
1 : Enabled
DTMF/DA1 selection bit
0 : DA1 function
1 : DTMF function
CTCSS/DA2 selection bit
0 : DA2 function
1 : CTCSS function
Low group ROM data selection bit
0 : Sine wave
1 : “0” fixed
High group ROM data selection bit
0 : Sine wave
1 : “0” fixed
High/Low group timer write control bit
0 : Write value in latch only
1 : Write value in latch and counter
CTCSS timer write control bit
0 : Write value in latch only
1 : Write value in latch and counter
b7
b0
D-A control register
(DACON : address 003616)
D-A2 conversion register (8)
R-2R resistor ladder
DA2 output enable bit
Data bus
P56/DA1
P57/DA2
5-bit adder
Selector
Low
group
ROM
5-bit 32
S
e
le
c
to
r
8-bit timer
D-A1 conversion register (8)
R-2R resistor ladder
DA1 output enable bit
XIN/2
Data bus
CTCSS
ROM
8-bit 64
10-bit timer
Selector
High
group
ROM
5-bit 32
*
S
e
le
c
to
r
S
e
le
c
to
r
* When DTMF is selected, the high-order 6 bits are automatically set
as the DTMF output.
The low-order 2 bits is set by writing data to the D-A1 conversion register.
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