參數(shù)資料
型號： M30880FJUGP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 6/60頁
文件大小： 458K
代理商： M30880FJUGP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3826 Group
15
I/O PORTS
Direction Registers
The I/O ports (ports P0, P1, P2, P4, P5, P6, P71–P77) have direc-
tion registers which determine the input/output direction of each
individual pin. (Ports P00–P07 are shared with bit 0 of the port P0
direction register, and ports P10–P15 shared with bit 0 of the port
P1 direction register.) Each bit in a direction register corresponds
to one pin, and each pin can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Port P3 Output Control Register
Bit 0 of the port P3 output control register (address 000716) en-
ables control of the output of ports P30–P37.
When the bit is set to “1”, the port output function is valid.
When resetting, bit 0 of the port P3 output control register is set to
“0” (the port output function is invalid) and pulled up.
Pull-up Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports P0 to P2, P4 to P6 can control pull-
up with a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
The PULL register A setting is invalid for pins set to segment out-
put with the segment output enable register.
Fig. 12 Structure of PULL register A and PULL register B
P00, P01 pull-up
P02, P03 pull-up
P04–P07 pull-up
P10–P13 pull-up
P14, P15 pull-up
P16, P17 pull-up
P20–P23 pull-up
P24–P27 pull-up
PULL register A
(PULLA : address 001616)
b7
b0
P41–P43 pull-up
P44–P47 pull-up
P50–P53 pull-up
P54–P57 pull-up
P60–P63 pull-up
P64–P67 pull-up
Not used (return “0” when read)
0 : Disable
1 : Enable
PULL register B
(PULLB : address 001716)
b7
b0
Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
相關(guān)PDF資料
PDF描述
M30882FHUGP 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP144
M30880FJTGP 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
M30880FWUGP 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
M30882FJTGP 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP144
M30882FWUGP 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP144
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