參數(shù)資料
型號(hào)： M30842MC-XXXGP
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, MROM, 32 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁(yè)數(shù)： 55/91頁(yè)
文件大?。?/td> 903K
代理商： M30842MC-XXXGP
58
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e parametric
limits
are
subject
to
change.
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory as instructed by software commands. This
rewrite control program must be transferred to internal RAM area
before it can be executed.
The MCU enters CPU rewrite mode by applying 4.5 V to 5.5 V to
the CNVSS pin and setting “1” to the CPU rewrite mode select bit
(bit 1 of address 0FFE16). Then, software commands can be ac-
cepted.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 62 shows the flash memory control register.
Bit 0 of the flash memory control register is the RY/BY status flag
used exclusively to read the operating status of the flash memory.
During programming and erase operations, it is “0” (busy). Other-
wise, it is “1” (ready).
Bit 1 of the flash memory control register is the CPU rewrite mode
select bit. When this bit is set to “1”, the MCU enters CPU rewrite
mode. And then, software commands can be accepted. In CPU re-
write mode, the CPU becomes unable to access the internal flash
memory directly. Therefore, use the control program in the internal
RAM for write to bit 1. To set this bit 1 to “1”, it is necessary to
write “0” and then write “1” in succession to bit 1. The bit can be
set to “0” by only writing “0”.
Bit 2 of the flash memory control register is the CPU rewrite mode
entry flag. This flag indicates “1” in CPU rewrite mode, so that
reading this flag can check whether CPU rewrite mode has been
entered or not.
Bit 3 of the flash memory control register is the flash memory reset
bit used to reset the control circuit of internal flash memory. This
bit is used when exiting CPU rewrite mode and when flash
memory access has failed. When the CPU rewrite mode select bit
is “1”, setting “1” for this bit resets the control circuit. To release
the reset, it is necessary to set this bit to “0”.
Bit 4 of the flash memory control register is the User area/Boot
area select bit. When this bit is set to “1”, Boot ROM area is ac-
cessed, and CPU rewrite mode in Boot ROM area is available. In
Boot mode, this bit is set to “1” automatically. Programming of this
bit must be executed on program of the internal RAM.
Figure 63 shows a flowchart for setting/releasing CPU rewrite
mode.
Fig. 62 Structure of flash memory control register
Flash memory control register (address 0FFE16)
FMCR
RY/BY status flag
0: Busy (being written or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User area / Boot area select bit
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (“0” at write, undefined at read)
b0
b7
Notes1: The contents of flash memory control register are “XXX00001” just after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession.
Use the control program in the RAM for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after
setting bit 3 to “1”.
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