![](http://datasheet.mmic.net.cn/30000/M30802MC-XXXGP_datasheet_2359337/M30802MC-XXXGP_141.png)
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Page 130
16. Serial I/O
p
u
o
r
G
0
8
/
C
6
1
M
UARTi transmit/receive mode register
Symbol
Address
When reset
UiMR(i=0,1)
036016, 036816
0016
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Must be fixed to 001
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set
0 1 1 : Must not be set
1 1 1 : Must not be set
b2 b1 b0
CKDIR
SMD1
SMD0
Serial I/O mode select bit
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
Parity enable bit
0 : Internal clock (Note 1)
1 : External clock (Note 2)
Stop bit length select bit
Odd/even parity select bit
Sleep select bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set
0 1 1 : Must not be set
1 1 1 : Must not be set
b2 b1 b0
0 : Internal clock
1 : External clock (Note 2)
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
Set to “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
UARTi transmit/receive mode register
Symbol
Address
When reset
UiMR (i=2 to 4)
033816, 032816, 02F816
0016
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
W
R
Must be fixed to 001
0 0 0 : Serial I/O invalid
0 1 0 : (Note)
0 1 1 : Must not be set
1 1 1 : Must not be set
b2 b1 b0
CKDIR
SMD1
SMD0
Serial I/O mode select bit
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
Parity enable bit
0 : Internal clock (Note 2)
1 : External clock (Note 3)
Stop bit length select bit
Odd/even parity select bit
TxD, RxD I/O polarity
reverse bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Usually set to “0”
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set
0 1 1 : Must not be set
1 1 1 : Must not be set
b2 b1 b0
0 : Internal clock
1 : External clock (Note 3)
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
0 : No reverse
1 : Reverse
Usually set to “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
Note 1: Bit 2 to bit 0 are set to “0102” when I
2C mode is used.
Note 2: Select CLK output by the corresponding function select registers A, B and C.
Note 3: Set the corresponding function select register A to the I/O port.
Note 1: Select CLK output by the corresponding function select registers A, B and C.
Note 2: Set the corresponding function select register A to the I/O port.
Figure 16.6 Serial I/O-related registers (2)