參數(shù)資料
型號(hào)： M30625FGPGP-D5
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP128
封裝： 14 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-128
文件頁(yè)數(shù)： 22/87頁(yè)
文件大?。?/td> 919K
代理商： M30625FGPGP-D5
M16C/62P Group (M16C/62P, M16C/62PT)
4. Special Function Register (SFR)
4
8
f
o
4
0
2
,
1
0
p
e
S
0
3
.
2
.
v
e
R
Z
0
3
2
0
-
1
0
B
3
0
J
E
R
page 29
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
Timer A0 Register
TA0
XXh
Timer A1 Register
TA1
XXh
Timer A2 Register
TA2
XXh
Timer B0 Register
TB0
XXh
Timer B1 Register
TB1
XXh
Timer B2 Register
TB2
XXh
Count Start Flag
TABSR
00h
One-Shot Start Flag
ONSF
00h
Timer A0 Mode Register
TA0MR
00h
Timer A1 Mode Register
TA1MR
00h
Timer A2 Mode Register
TA2MR
00h
Timer B0 Mode Register
TB0MR
00XX0000b
Timer B1 Mode Register
TB1MR
00XX0000b
Timer B2 Mode Register
TB2MR
00XX0000b
Up-Down Flag
UDF
00h (2)
Timer A3 Register
TA3
XXh
Timer A4 Register
TA4
XXh
Timer A3 Mode Register
TA3MR
00h
Timer A4 Mode Register
TA4MR
00h
Trigger Select Register
TRGSR
00h
Clock Prescaler Reset Fag
CPSRF
0XXXXXXXb
UART0 Transmit/Receive Mode Register
U0MR
00h
UART0 Transmit Buffer Register
U0TB
XXh
UART0 Receive Buffer Register
U0RB
XXh
UART1 Transmit/Receive Mode Register
U1MR
00h
UART1 Transmit Buffer Register
U1TB
XXh
UART1 Receive Buffer Register
U1RB
XXh
UART0 Bit Rate Generator
U0BRG
XXh
UART0 Transmit/Receive Control Register 0
U0C0
00001000b
UART0 Transmit/Receive Control Register 1
U0C1
00XX0010b
UART1 Bit Rate Generator
U1BRG
XXh
UART1 Transmit/Receive Control Register 0
U1C0
00001000b
UART1 Transmit/Receive Control Register 1
U1C1
00XX0010b
DMA1 Request Cause Select Register
DM1SL
00h
DMA0 Request Cause Select Register
DM0SL
00h
CRC Data Register
CRCD
XXh
CRC Input Register
CRCIN
XXh
UART Transmit/Receive Control Register 2
UCON
X0000000b
NOTES :
1.The blank areas are reserved and cannot be accessed by users.
2. Bits 7 to 5 in the Up-down flag are “0” by reset. However, The values in these bits when read are indeterminate.
X : Nothing is mapped to this bit
Timer B2 Special Mode Register
TB2SC
XXXXXX00b
Address
Register
Symbol
After Reset
Table 4.5 SFR information (5)(1)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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