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| 型號(hào)： | M30622MWP-XXXGP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁數(shù)： | 43/87頁 |
| 文件大小： | 901K |
| 代理商： | M30622MWP-XXXGP |
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M16C/62 Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62P)
4
8
f
3
0
0
2
,
0
.
o
N
0
1
e
R
page 43
Table 5.29 Memory Expansion and Microprocessor Modes
(for 2- to 3-wait setting, external area access and multiplex bus selection)
t
h(BCLK-AD)
Address output hold time (refers to BCLK)
t
h(RD-AD)
Address output hold time (refers to RD)
t
h(WR-AD)
Address output hold time (refers to WR)
V
CC1
= V
CC2
= 5V
Switching Characteristics
(V
CC1
= V
CC2
= 5V, V
SS
= 0V, at Topr = – 20 to 85
o
C / – 40 to 85
o
C unless otherwise specified)
4
ns
ns
ns
t
d(BCLK-CS)
t
h(BCLK-CS)
t
h(RD-CS)
t
h(WR-CS)
Chip select output delay time
Chip select output hold time (refers to BCLK)
Chip select output hold time (refers to RD)
Chip select output hold time (refers to WR)
25
ns
ns
ns
ns
4
(Note 1)
t
d(BCLK-RD)
t
h(BCLK-RD)
t
d(BCLK-WR)
t
h(BCLK-WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
25
ns
ns
ns
ns
0
(Note 1)
25
t
d(BCLK-DB)
t
h(BCLK-DB)
t
d(DB-WR)
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK)
Data output delay time (refers to WR)
40
ns
ns
ns
4
(Note 2)
0
(Note 1)
(Note 1)
t
h(WR-DB)
t
d(BCLK-HLDA)
Data output hold time (refers to WR)
HLDA output delay time
ns
ns
(Note 1)
1. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 10
9
[ns]
2. Calculated according to the BCLK frequency as follows:
f(BCLK)
(n
–
0.5) X 10
9
–
40
[ns]
3. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 10
9
–
25
[ns]
n is
“
2
”
for 2-wait setting,
“
3
”
for 3-wait setting.
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
d(AD-ALE)
ALE signal output delay time (refers to BCLK)
ALE signal output hold time (refers to BCLK)
ALE signal output delay time (refers to Address)
15
ns
ns
ns
–
4
t
h(ALE-AD)
t
d(AD-RD)
t
d(AD-WR)
t
dZ(RD-AD)
ALE signal output hold time (refers to Adderss)
RD signal output delay from the end of Adress
WR signal output delay from the end of Adress
Address output floating start time
ns
ns
ns
ns
0
0
8
(Note 3)
(Note 4)
–
10
4. Calculated according to the BCLK frequency as follows:
f(BCLK)
0.5 X 10
9
[ns]
–
15
NOTES:
40
See
Figure 5.1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30622S4-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY |
| M30622S4-XXXFS | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY |
| M30622S4-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY |
| M30622S8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY |
| M30622S8-XXXFS | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY |
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