參數(shù)資料
型號: M30622MWP-XXXFP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機
文件頁數(shù): 85/87頁
文件大?。?/td> 901K
代理商: M30622MWP-XXXFP
REVISION HISTORY
Rev.
Date
Description
Page
2
4-5
14-19
Summary
A-1
M16C/62 Group (M16C/62P, M16C/62PT) Data Sheet
1.10 May/28/Y03
(Continued)
2.00 Oct./29/Y03
Table 1.1.1 is partly revised.
Table 1.1.2 and 1.1.3 is partly revised.
SFR is partly revised.
Note 1
is partly revised.
Table 1.5.3 is partly revised.
Table 1.5.5 is partly revised.
Table 1.5.6 is added.
Table 1.5.9 is partly revised.
Notes 1 and 2 in Table 1.5.26 is partly revised.
Notes 1 in Table 1.5.27 is partly revised.
Note 3 is added to
Data output hold time (refers to BCLK)
in Table 1.5.26 and
1.5.27.
Note 4 is added to
th(ALE-AD)
in Table 1.5.28.
Switching Characteristics is partly revised.
th(WR-AD) and th(WR-DB) in Figure 1.5.5 to 1.5.8 is partly revised.
th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.9 to 1.5.10 is
partly revised.
Note 2 is added to Table 1.5.29.
Notes 1 and 2 in Table 1.5.45 is partly revised.
Notes 1 in Table 1.5.46 is partly revised.
Note 3 is added to
Data output hold time (refers to BCLK)
in Table 1.5.45 and
1.5.46.
Note 4 is added to
th(ALE-AD)
in Table 1.5.47.
Switching Characteristics is partly revised.
th(WR-AD) and th(WR-DB) in Figure 1.5.15 to 1.5.18 is partly revised.
th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.19 to 1.5.20 is
partly revised.
Since high reliability version is added, a group name is revised.
M16C/62 Group (M16C/62P)
M16C/62 Group (M16C/62P, M16C/62PT)
Table 1.1 to 1.3 are revised.
Note 3 is partly revised.
Figure 1.2 Note5 is deleted.
Table 1.4 to 1.7 Product List is partly revised.
Table 1.8 and Figure 1.4 are added.
Figure 1.5 to 1.9 ZP is added.
Table 1.10 and 1.12 ZP is added to timer A.
Table 1.11 and 1.13 VCC1 is added to VREF.
Table 5.1 is revised.
Table 5.2 and 5.3 are revised.
Table 5.4 A-D Conversion Characteristics is revised.
Table 5.5 D-A Conversion Characteristics revised.
Table 5.6 to 5.7 and table 5.54 to 5.55 are revised.
Table 5.11 is revised.
Table 5.14 and 5.33 HLDA output deley time is deleted.
Figure 5.1 is partly revised.
Table 5.27 to 5.29 and table 5.46 to 48 HLDA output deley time is added.
Figure 5.2 Timing Diagram (1) X
IN
input is added.
22
23
24
30
31
30-31
32
30-32
36-39
40-41
42
47
48
47-48
49
47-49
53-56
57-58
-
2-4
6
7-9
11
12-15
17,19
18,20
30
31-32
33
34,74
36
38,55
41
41-43,
58-60
44
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