參數(shù)資料
型號： M30622MHP-XXXFP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機
文件頁數(shù)： 41/87頁
文件大?。?/td> 901K
代理商： M30622MHP-XXXFP
M16C/62 Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62P)
4
8
f
3
0
0
2
,
0
.
o
N
0
1
e
R
page 41
Table 5.27 Memory Expansion and Microprocessor Modes (for setting with no wait)
y
m
b
o
l
P
r
a
m
e
t
e
r
(
B
C
L
K
-
A
D
)
A
d
r
e
s
s
o
u
t
p
u
t
d
e
l
a
y
t
i
m
e
t
h
(
B
C
L
K
-
A
D
)
A
d
r
e
s
s
o
u
t
p
u
t
h
o
l
d
t
i
m
e
(
r
e
f
e
r
s
t
o
B
C
L
t
h
(
R
D
-
A
D
)
A
d
r
e
s
s
o
u
t
p
u
t
h
o
l
d
t
i
m
e
(
r
e
f
e
r
s
t
o
R
D
)
t
h
(
W
R
-
A
D
)
A
d
r
e
s
s
o
u
t
p
u
t
h
o
l
d
t
i
m
e
(
r
e
f
e
r
s
t
o
W
R
V
CC1
= V
CC2
= 5V
Switching Characteristics
(V
CC1
= V
CC2
= 5V, V
SS
= 0V, at Topr = – 20 to 85
o
C / – 40 to 85
o
C unless otherwise specified)
S
Standard
Min.
Measuring condition
M
2
a
x
.
a
U
n
i
t
t
d
d
d
d
d
5
n
n
n
n
s
s
s
s
K
)
4
0
t
h
t
d
t
h
t
d
t
h
t
d
t
h
t
d(BCLK-DB)
t
h
(
B
C
L
t
d(DB-WR)
(
B
C
L
K
-
C
S
)
C
A
A
R
R
W
W
Data output delay time (refers to BCLK)
D
a
t
a
o
u
t
p
u
t
h
o
l
d
t
i
m
Data output delay time (refers to WR)
h
L
L
D
D
i
E
E
R
R
p
s
s
s
s
s
s
s
e
i
g
i
g
g
g
i
g
i
g
l
n
n
a
a
n
n
e
c
a
a
l
l
a
a
t
l
l
o
o
o
o
o
o
u
u
o
u
u
u
t
t
u
u
t
p
t
p
p
p
t
p
t
p
p
u
u
u
t
t
u
u
t
t
d
h
t
t
d
h
e
o
d
h
h
o
e
o
l
a
l
d
e
l
o
l
l
a
l
d
y
a
d
d
t
t
t
t
i
y
t
i
t
i
m
i
m
m
t
i
i
m
m
i
m
e
(
r
e
f
e
r
s
t
o
B
C
L
K
)
4
n
n
n
n
n
n
n
ns
n
ns
s
s
s
s
s
s
s
(
B
C
L
K
-
A
L
E
)
t
t
l
y
e
15
(
B
C
L
K
-
A
L
E
)
e
e
–
4
(
B
C
L
K
-
R
D
)
i
i
n
n
u
u
2
5
(
B
C
L
K
-
R
D
)
e
m
e
0
(
B
C
L
K
-
W
R
)
l
l
e
2
5
(
B
C
L
K
-
W
R
)
0
40
K
-
D
B
)
e
(
r
e
f
e
r
s
t
o
B
C
L
K
)
(
3
)
4
s
t
h(WR-DB)
t
d(
B
C
Data output hold time (refers to WR)
(3)
HLDA output delay time
ns
ns
1. Calculated according to the BCLK frequency as follows:
f(
B
C
L
K
)
0.5 X 10
9
–
40
[ns]
t
d
(
B
C
L
K
-
C
S
)
C
h
i
p
s
e
l
e
c
t
o
u
t
p
u
t
d
e
l
a
y
t
i
m
e
2
5
n
s
)
(Note 2)
3. This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t =
–
CR X ln (1
–
V
OL
/ V
CC2
)
by a circuit of the right figure.
For example, when V
OL
= 0.2V
CC2
, C = 30pF, R = 1k
, hold time
of output
“
L
”
level is
t =
–
30pF X 1k
X ln (1
–
0.2V
CC2
/ V
CC2
)
= 6.7ns.
DBi
R
C
(Note 1)
(Note 2)
2. Calculated according to the BCLK frequency as follows:
.
5
X
1
0
9
[ns]
f(BCLK)
0
f(
B
C
L
K
)
i
s
1
2
.
5
M
H
z
o
r
l
e
s
s
.
–
1
0
N
O
T
E
S
:
40
L
K
-
H
L
D
A
)
See
Figure 5.1
P6
P7
P8
P9
P10
P0
P1
P2
P3
P4
P5
30pF
P11
P12
P13
P14
Figure 5.1 Ports P0 to P14 Measurement Circuit
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