參數(shù)資料
型號(hào): EDD1216AJTA-7B-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M bits DDR SDRAM
中文描述: 8M X 16 DDR DRAM, 0.75 ns, PDSO66
封裝: ROHS COMPLIANT, PLASTIC, TSOP2-66
文件頁數(shù): 15/52頁
文件大小: 513K
代理商: EDD1216AJTA-7B-E
EDD1216AJTA
Data Sheet E0972E30 (Ver. 3.0)
15
CKE (input pin)
This pin determines whether or not the next CK is valid. If CKE is high, the next CK rising edge is valid. If CKE is
low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when
the CKE is driven low and exited when it resumes to high. CKE must be maintained high throughout read or write
access.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper
hold time tIH.
UDM, LDM (input pin)
DMs are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and
VREF. DMs provide the byte mask function. When DM = high, the data input at the same timing are masked while
the internal burst counter will be count up. In
×
16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM
controls the upper byte (DQ8 to DQ15) of write data.
DQ0 to DQ15 (input/output pins)
Data is input to and output from these pins.
UDQS, LDQS (input and output pin)
DQS provides the read data strobes (as output) and the write data strobes (as input). In
×
16 products, LDQS is the
lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
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