參數(shù)資料
型號: M30620SAGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 16 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 30/40頁
文件大?。?/td> 3893K
代理商: M30620SAGP
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
33
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK
cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring
to the recommended operating conditions (main clock input oscillation frequency) of the electric character-
________
istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’s
bits 4 to 7 must be set to “0”.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in
one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
insert a software wait if using the multiplex bus to access the external memory area.
Table 1.9.8 shows the software wait and bus cycles. Figure 1.9.6 shows example of bus timing when
using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Area
Bus status
Wait bit
Bits 4 to 7 of chip select
control register
Bus cycle
Invalid
1
2 BCLK cycles
External
memory
area
Separate bus
0
1
1 BCLK cycle
Separate bus
0
2 BCLK cycles
Separate bus
1
0 (Note)
2 BCLK cycles
Multiplex bus
0
3 BCLK cycles
Multiplex bus
1
3 BCLK cycles
0 (Note)
SFR
Internal
ROM/RAM
0
Invalid
1 BCLK cycle
Invalid
2 BCLK cycles
Note: When using the RDY signal, always set to “0”.
Table 1.9.8. Software waits and bus cycles
(8) BCLK output
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note).
When set to “1”, the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30620SFP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30620SGP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY
M30620SPFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30620SPFP#U3 制造商:Renesas Electronics Corporation 功能描述:
M30620SPFP#U3C 功能描述:IC M16C/62P MCU ROMLESS 100QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器, 系列:M16C™ M16C/60/62P 產(chǎn)品培訓(xùn)模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標(biāo)準(zhǔn)包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI,I²C,IEBus,IrDA,SIO,UART/USART 外圍設(shè)備:DMA,POR,PWM,WDT 輸入/輸出數(shù):121 程序存儲(chǔ)器容量:384KB(384K x 8) 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 34x10b,D/A 2x8b 振蕩器型:內(nèi)部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 產(chǎn)品目錄頁面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87