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Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
46
Figure 1.13.3. Interrupt control registers
Symbol
INTiIC(i=0 to 2)
Address
When reset
XX00X000
2
005D
16
to 005F
16
Bit name
Function
Bit symbol
ILVL0
W
R
b7
b6
b5
0
b4
b3
b2
b1
b0
AA
AA
IR
POL
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
ILVL1
ILVL2
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
(Note 1)
A
Interrupt control register
b7
b6
b5
b4
b3
b2
b1
b0
AAAA
AAAA
Bit name
Function
Bit symbol
W
R
Symbol
BCNIC
DMiIC(i=0, 1)
KUPIC
ADIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
Address
When reset
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
XXXXX000
2
004A
16
004B
16
, 004C
16
004D
16
004E
16
0051
16
, 0053
16
, 004F
16
0052
16
, 0054
16
, 0050
16
0055
16
to 0059
16
005A
16
to 005C
16
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
AA
AA
AA
AA
AA
AA
AA
A
A
AA
A
A
A
A
A