![](http://datasheet.mmic.net.cn/30000/M30280M8V-XXXHP_datasheet_2358818/M30280M8V-XXXHP_128.png)
12. Timer B
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Item
Specification
Count source
External signals input to TBiIN pin (i=0 to 2) (effective edge can be selected
in program)
Timer Bj overflow or underflow (j=i-1, except j=2 if i=0)
Count operation
Decrement
When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1)
n: set value of TBi register
000016 to FFFF16
Count start condition
Set TBiS bit(1) to 1 (start counting)
Count stop condition
Set TBiS bit to 0 (stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Count source input
Read from timer
Count value can be read by reading TBi register
Write to timer
When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
NOTE:
1. Bits TB2S to TB0S are assigned to the bit 7 to bit 5 in the TABSR register.
12.2.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers (see Table 12.7). Figure 12.19 shows the TBiMR register in event counter mode.
Table 12.7 Specifications in Event Counter Mode
Figure 12.19 TBiMR Register in Event Counter Mode
Timer Bi Mode Register (i=0 to 2)
Symbol
Address
After Reset
TB0MR to TB2MR
039B16 to 039D16
00XX00002
Bit Name
Function
Bit Symbol
RW
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1: Event counter mode
b1 b0
TMOD1
TMOD0
MR0
Count polarity select bit (1)
MR2
MR1
MR3
TCK1
TCK0
01
0 0: Counts external signal's
falling edges
0 1: Counts external signal's rising
edges
1 0: Counts external signal's
falling and rising edges
1 1: Do not set
b3 b2
No effect in event counter mode
Can be set to 0 or 1
Event clock select
0 : Input from TBiIN pin (2)
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0)
RW
RO
TB0MR register
Set to 0 in timer mode
TB1MR, TB2MR registers
Nothing is assigned. If necessary, set to 0. When read, the
content is undefined
NOTES:
1. Effective when the TCK1 bit is set to 0 (input from TBiIN pin). If the TCK1 bit is set to 1 (TBj overflow or underflow),
these bits can be set to 0 or 1.
2. The port direction bit for the TBiIN pin must be set to 0 (= input mode).
When write in event counter mode, set to 0. When read in event
counter mode, the content is undefined