
13. Serial I/O
page 135
9
2
3
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7
0
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,
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R
0
2
0
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2
0
2
0
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9
0
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6
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/
C
6
1
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,
B
6
2
/
C
6
1
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,
A
6
2
/
C
6
1
M
(
p
u
o
r
G
A
6
2
/
C
6
1
M
SP
PAR
2SP
1SP
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous
type
Clock
synchronous type
Data bus low-order bits
TxD2
UARTi transmit register
PAR
disabled
PAR
enabled
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 transmit
buffer register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART2 receive
buffer register
UARTi receive register
2SP
1SP
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous type
Clock
synchronous type
RxD2
UART
(8 bits)
UART
(9 bits)
Address 037E16
Address 037F16
Address 037A16
Address 037B16
Data bus high-order bits
D7
D6
D5
D4
D3
D2
D1
D0
D8
000
0000
SP
PAR
0
Reverse
No reverse
Error signal
output circuit
RxD data
reverse circuit
Error signal output
enable
Error signal output
disable
Reverse
No reverse
Logic reverse circuit + MSB/LSB conversion circuit
PAR
enabled
PAR
disabled
UART
Clock
synchronous
type
TxD data
reverse circuit
SP: Stop bit
PAR: Parity bit
STPS=0
STPS=1
PRYE=0
PRYE=1
STPS=0
STPS=1
PRYE=0
PRYE=1
IOPOL=0
IOPOL=1
IOPOL
=0
IOPOL
=1
U2ERE
=0
U2ERE
=1
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bit in the U2MR register
U2ERE : Bit in the U2C1 register
0
1
SMD2 to SMD0
11
0
1
SMD2 to SMD0
1
0
Figure 13.1.3. Block diagram of UART2 transmit/receive unit