參數(shù)資料
型號: M30240F2
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁數(shù): 24/142頁
文件大?。?/td> 1637K
代理商: M30240F2
1-24
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Clock Control
2.8 Clock Control
Figure 1.12 shows the block diagram of the clock-generating circuit.
Figure 1.12: Clock-generating circuit
The following paragraphs describe the clocks generated by the clock-generating circuit.
2.8.1 Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by
8 to the internal clock
Φ
. The clock can be stopped using the main clock stop bit (bit 5 at address
0006
16
). Stopping the clock reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the f(Xout)
pin can be reduced using the f(Xin)-f(Xout) drive capacity select bit (bit 5 at address 0007
16
). Reducing
the drive capacity of the f(Xout) pin reduces the power dissipation. This bit defaults to “1” when shifting
to stop mode and after a reset.
2.8.2 Internal clock
Φ
The internal clock
Φ
is the clock that drives the CPU, and is either the main clock or is derived by di-
viding the main clock by 2, 4, 8, or 16. The internal clock
Φ
is derived by dividing the main clock by 8
after a reset.
When shifting to stop mode, the main clock division select bit (bit 6 at 0006
16
) is set to “1”.
CM0i : Bit i at address 0006
16
CM1i : Bit i at address 0007
16
FSCCRi: Bit i at address 03DB
16
WAIT instruction
CM02
Q
S
R
NMI
Interrupt request
level judgment
output
RESET
Software reset
f
AD
Divider
a
d
1/2
1/2
1/2
1/2
CM06=0
CM17,CM16=00
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=10
CM06=1
CM06=0
CM17,CM16=11
d
a
Details of divider
c
b
b
1/2
c
f
1
f
32
SIO2
f
8
SIO2
f
1
SIO2
f
8
f
32
φ
X
OUT
Main clock
CM10 “1”
Write signal
Q
S
R
X
IN
Frequency
Synthesizer
Circuit
f
usb (48MHz)
FSCCR0=1
FSCCR0=0
Internal clock
φ
fsyn
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