參數(shù)資料
型號： M30240E3-XXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁數(shù)： 98/142頁
文件大?。?/td> 1637K
代理商： M30240E3-XXXFP
1-98
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
UART0 through UART2
Figure 1.88: UARTi transmit/receive mode register in UART mode
Table 1.28:
Specifications of UART Mode (2)
Item
Specification
Select
function
Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave micro-computers
Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed.
TxD, RxD I/O polarity switch
This function is reversing TxD port output and RxD port input. All I/O data level is reversed.
Symbol
UiMR(i=0,1)
Address
03A0
16
, 03A8
16
When reset
00
16
CKDIR
UARTi transmit / receive mode registers
Internal / external clock
select bit
Stop bit length select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Bit name
Function
Bit symbol
W
R
A
A
A
A
A
A
b7
b6
b5
b4
b3
b2
b1
b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Odd / even parity
select bit
Parity enable bit
Sleep select bit
Symbol
U2MR
Address
0378
16
When reset
00
16
CKDIR
UART2 transmit / receive mode register
Internal / external clock
select bit
Stop bit length select bit
STPS
PRY
PRYE
IOPOL
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Bit name
Function
Bit symbol
W
R
A
A
A
A
A
b7
b6
b5
b4
b3
b2
b1
b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Odd / even parity
select bit
Parity enable bit
TxD, RxD I/O polarity
reverse bit (Note)
A
A
A
A
A
A
Note: Usually set to “0”.
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