
Unde
Clock asynchronous serial I/O (UART) mode
deeopmen
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
87
Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Figure 1.80. Typical transmit timings in UART mode
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag
(TXEPT)
Start
bit
Parity
bit
TxDi
The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = “1”.
“1”
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f
1
, f
8
, f
32
, f
c
)
f
EXT
: frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxDi
Transmit register
empty flag
(TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings :
Parity is disabled.
Two stop bits.
Transmit interrupt cause select bit = “0”.
Transfer clock
Tc
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f
1
, f
8
, f
32
)
f
EXT
: frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR)
“0”
“1”
Shown in ( ) are bit symbols.
Shown in ( ) are bit symbols.
Tc
Transfer clock
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
SP
ST
P
SP
D
0
D
1
ST
Stopped pulsing because transmit enable bit = “0”
Stop
bit
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
Data is set in UARTi transmit buffer register
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
SP
D
8
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
D
8
D
0
D
1
ST
SPSP
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop
bit
bit
Stop
Data is set in UARTi transmit buffer register.
“0”
SP
Cleared to “0” when interrupt request is accepted, or cleared by software