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參數(shù)資料
| 型號： | M30102M3T-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 102/166頁 |
| 文件大?。?/td> | 2060K |
| 代理商： | M30102M3T-XXXFP |
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Under
development
Tentative Specifications REV.E1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
37
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
Reset
____________
Reset occurs if an “L” is input to the RESET pin.
UART0 receive interrupt
UART0 receive interrupt occurs when UART1 is received. This interrupt can be enabled with bit 2 of
_______
the INT0 input filter select register (address 001E16).
This interrupt is exclusively for the debugger, do not use it in other circumstances.
_______
DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
Oscillation stop detection/watchdog timer interrupt
Generated by the oscillation stop detection or watchdog timer.
Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag
(D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is
set, no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector table is
_______
the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O
interrupts are maskable interrupts.
Key-input interrupt
___
A key-input interrupt occurs if a falling or rising edge is input to the KI pin.
A-D conversion interrupt
This is an interrupt that the A-D converter generates.
UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
Timer X interrupt
This is an interrupts that timer X generates.
Timer Y interrupt
This is an interrupt that timer Y generates.
Timer Z interrupt
This is an interrupt that timer Z generates.
Timer C interrupt
This is an interrupt that timer C generates.
CNTR0 interrupt
This interrupt occurs if a falling or rising edge is input to the CNTR0 pin.
TCIN interrupt
This interrupt occurs if a falling edge, rising edge or both edges are input to the TCIN pin. This interrupt
also occurs with the RING512.
________
_______
INT0 to INT3 interrupt
______
_______
INT0 to INT2 interrupts occur if any one of a rising edge, a falling edge or a both-edge is input to the
______
_______
______
INT pin. INT3 inerrupt occurs if either a falling edge or a both-edge is input to the INT pin.
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