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參數(shù)資料
| 型號： | M2Y51264TU88A2G-37B |
| 廠商： | NANYA TECHNOLOGY CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 1/19頁 |
| 文件大?。?/td> | 444K |
| 代理商： | M2Y51264TU88A2G-37B |
M2Y51264TU88A2G/ M2Y1G64TU8HA2G
512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.0
1
6/2006
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
240pin Unbuffered DDR2 SDRAM MODULE
Based on 64Mx8 DDR2 SDRAM
Features
JEDEC Standard 240-pin Dual In-Line Memory Module
64Mx64 and 128Mx64 DDR2 Unbuffered DIMM based on
64Mx8 DDR2 SDRAM
Performance:
PC2-4200 PC2-5300
Speed Sort
37B
3C
DIMM
Latency*
4
5
Unit
f CK Clock Frequency
266
333
MHz
t CK Clock Cycle
3.75
3
ns
f DQ DQ Burst Frequency
533
667
MHz
Intended for 266MHz and 333MHz applications
Inputs and outputs are SSTL-18 compatible
VDD = VDDQ = 1.8Volt ± 0.1
SDRAMs have 4 internal banks for concurrent operation
Differential clock inputs
Data is read or written on both clock edges
Bi-directional data strobe with one clock cycle preamble and
one-half clock post-amble
Address and control signals are fully synchronous to positive
clock edge
Write Latency = Read Latency - 1
Programmable Operation:
- Device
Latency: 3, 4, 5
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
Auto Refresh (CBR) and Self Refresh Modes
Automatic and controlled precharge commands
14/10/1 Addressing (row/column/bank) – 512MB
14/10/2 Addressing (row/column/bank) – 1GB
7.8 s Max. Average Periodic Refresh Interval
Serial Presence Detect
On Die Termination (ODT)
Gold contacts
SDRAMs in TSOP Package
RoHS Compliance
Description
M2Y51264TU88A2G and M2Y1G64TU8HA2G are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line
Memory Module (UDIMM), organized as a one-rank 64Mx64 and two ranks 128Mx64 high-speed memory array. Modules use eight
64Mx8 (M2Y51264TU88A2G) and sixteen 64Mx8 (M2Y1G64TU8HA2G) DDR2 SDRAMs in TSOP packages. These DIMMs are
manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes
electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25”
long space-saving footprint.
The DIMM is intended for use in applications operating up to 266MHZ (333MHz) clock speeds and achieves high-speed data transfer
rates of up to 533MHz (667MHz). Prior to any access operation, the device
latency and burst / length / operation type must be
programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
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