參數(shù)資料
型號(hào): M2S28D20ATP-75
廠商: Mitsubishi Electric Corporation
英文描述: 128M Double Data Rate Synchronous DRAM
中文描述: 128M的雙數(shù)據(jù)速率同步DRAM
文件頁(yè)數(shù): 26/36頁(yè)
文件大?。?/td> 1216K
代理商: M2S28D20ATP-75
26
MITSUBISHI ELECTRIC
Jun,'00
Preliminary
MITSUBISHI LSIs
DDR SDRAM (Rev.0.1)
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
Read Interrupted by Read (BL=8, CL=2)
Command
A0-9,11
A10
BA0,1
DQ
Yi
READ READ
READ
READ
Yj
Yk
Yl
0
0
0
0
00
10
00
01
DQS
Qai0 Qai1 Qaj0 Qaj1
Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2
Qal3 Qal4 Qal5 Qal6 Qal7
/CLK
CLK
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to PRE interval determines valid data length to be output. The figure below
shows examples of BL=8.
Read Interrupted by Precharge (BL=8)
/CLK
CLK
CL=2.5
Command
DQS
Command
DQ
Command
DQ
Q0
Q1
Q2
Q3
Q0
Q1
DQ
Q0
Q1
Q2
Q3
Q4
Q5
PRE
READ
READ
PRE
READ PRE
DQS
DQS
相關(guān)PDF資料
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M2S28D30ATP 128M Double Data Rate Synchronous DRAM
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M2S28D40ATP-10 128M Double Data Rate Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M2S28D30ATP 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM
M2S28D30ATP-10 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM
M2S28D30ATP-75 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM
M2S28D40ATP 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM
M2S28D40ATP-10 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:128M Double Data Rate Synchronous DRAM