參數資料
型號： M29DW640F70N6F
廠商： STMICROELECTRONICS
元件分類： PROM
英文描述： 4M X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝： 12 X 20 MM, LEAD FREE, PLASTIC, TSOP-48
文件頁數： 9/74頁
文件大小： 556K
代理商： M29DW640F70N6F
M29DW640F
Bus operations
3
Bus operations
There are five standard bus operations that control the device. These are Bus Read
(Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
Using the multiple bank architecture of the M29DW640F, while programming or erasing is
underway in one group of banks (from 1 to 3), reading can be conducted in any of the other
banks. Write operations are only allowed in one bank at a time.
See Table 4 and Table 5, Bus operations, for a summary. Typically glitches of less than 5ns
on Chip Enable, Write Enable, and Reset pins are ignored by the memory and do not affect
bus operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. To speed up the read operation the memory array can be read in Page mode
where data is internally read and stored in a page buffer. The Page has a size of 8 Words
and is addressed by the address inputs A0-A2.
A valid Bus Read operation involves setting the desired address on the Address Inputs,
applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the value, see Figure 10: Random Read AC
for details of when the output becomes valid.
3.2
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure 12 and Figure 13, Write AC waveforms,
and Table 17 and Table 18, Write AC characteristics, for details of the timing requirements.
3.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the
Standby current level see Table 15: DC characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, ICC3, for Program or Erase operations until the operation completes.
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相關代理商/技術參數
參數描述
M29DW640F70N6T 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640F70ZE1 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640F70ZE1E 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640F70ZE1F 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
M29DW640F70ZE1T 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:64 Mbit (8Mb x8 or 4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
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