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參數(shù)資料
| 型號(hào)： | M28.173A |
| 廠商： | Intersil Corporation |
| 英文描述： | Plastic Packages for Integrated Circuits |
| 中文描述： | 集成電路塑料封裝 |
| 文件頁(yè)數(shù)： | 1/1頁(yè) |
| 文件大?。?/td> | 13K |
| 代理商： | M28.173A |
52
Thin Shrink Small Outline Exposed Pad Plastic Packages (EPTSSOP)
α
INDEX
AREA
E1
D
N
1
2
3
-B-
0.10(0.004)
C A
M
B S
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E
0.25(0.010)
B
M
M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
TOP VIEW
P1
1
2
3
P
BOTTOM VIEW
N
M28.173A
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.378
0.386
9.60
9.80
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
N
α
P
28
28
7
0
o
8
o
0
o
8
o
-
-
0.138
-
3.50
11
P1
-
0.118
-
3.0
11
Rev. 1 6/99
NOTES:
1. Thesepackagedimensionsarewithinallowabledimensions
of JEDEC MO-153-AET, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M
-
1982.
3. Dimension “D” does not include mold flash, protrusions or
gate burrs. Mold flash, protrusion and gate burrs shall not
exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protru-
sions. Interlead flash and protrusions shall not exceed
0.15mm (0.006 inch) per side.
5. The chamfer on the body is optional. If it is not present, a vi-
sual index feature must be located within the crosshatched
area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allow-
able dambar protrusion shall be 0.08mm (0.003 inch) total
in excess of “b” dimension at maximum material condition.
Minimum space between protrusion and adjacent lead is
0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch di-
mensions are not necessarily exact. (Angles in degrees)
11. Dimensions “P” and “P1” are thermal and/or electrical en-
hanced variations. Values shown are maximum size of ex-
posed pad within lead count and body size.
Plastic Packages for Integrated Circuits
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