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參數資料
| 型號： | M27V102-90B6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 64K X 16 OTPROM, 90 ns, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-40 |
| 文件頁數： | 11/15頁 |
| 文件大?。?/td> | 169K |
| 代理商： | M27V102-90B6 |
Obsolete
Product(s)
- Obsolete
Product(s)
5/15
M27V102
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = VCC)
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
Table 8A. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = VCC)
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0V
≤ VIN ≤ VCC
±10
A
ILO
Output Leakage Current
0V
≤ VOUT ≤ VCC
±10
A
ICC
Supply Current
E = VIL, G = VIL, IOUT = 0mA,
f = 5MHz, VCC ≤ 3.6V
15
mA
ICC1
Supply Current (Standby) TTL
E = VIH
1mA
ICC2
Supply Current (Standby) CMOS
E > VCC – 0.2V, VCC ≤ 3.6V
20
A
IPP
Program Current
VPP = VCC
10
A
VIL
Input Low Voltage
–0.3
0.8
V
VIH
(2)
Input High Voltage
2
VCC + 1
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage TTL
IOH = –400A
2.4
V
Output High Voltage CMOS
IOH = –100A
VCC – 0.7V
V
Symbol
Alt
Parameter
Test Condition
M27V102
Unit
-90 (3)
-100
Min
Max
Min
Max
tAVQV
tACC
Address Valid to Output Valid
E = VIL, G = VIL
90
100
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
90
100
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
45
50
ns
tEHQZ
(2)
tDF
Chip Enable High to Output Hi-Z
G = VIL
030030
ns
tGHQZ
(2)
tDF
Output Enable High to Output Hi-Z
E = VIL
030030
ns
tAXQX
tOH
Address Transition to Output
Transition
E = VIL, G = VIL
00
ns
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
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相關代理商/技術參數 |
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| M27V102-90B6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 64Kb x 16 Low Voltage UV EPROM and OTP EPROM |
| M27V102-90F1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 64Kb x 16 Low Voltage UV EPROM and OTP EPROM |
| M27V102-90F6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 64Kb x 16 Low Voltage UV EPROM and OTP EPROM |
| M27V102-90K1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 64Kb x 16 Low Voltage UV EPROM and OTP EPROM |
| M27V102-90K6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 64Kb x 16 Low Voltage UV EPROM and OTP EPROM |
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