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參數(shù)資料
| 型號： | M27C516-10C1TR |
| 廠商： | 意法半導體 |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RW-S Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 48V; Output Voltage (Vdc): 09V; Power: 2W; DIP24 Low Profile Miniature Package; 1kVDC Isolation; Feedback Regulated Output; 2:1 Wide Range Voltage Input; Continuous Short Circuit Protection; Less than 7mm Height; SMD Pinning Option; Efficiency to 87% |
| 中文描述： | 512千位的32KB x16檢察官辦公室存儲器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 93K |
| 代理商： | M27C516-10C1TR |
tAVPL
VALID
AI00936
A0-A14
Q0-Q15
VPP
VCC
P
G
DATA IN
DATA OUT
E
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 6. Programmingand Verify Modes AC Waveforms
AI00707C
n = 0
Last
Addr
VERIFY
P = 100
μ
s Pulse
++n
= 25
++ Addr
VCC= 6.25V, VPP= 12.75V
FAIL
CHECK ALL WORDS
1st: VCC= 6V
2nd: VCC= 4.2V
YES
NO
YES
NO
YES
NO
Figure 7. ProgrammingFlowchart
PRESTOII ProgrammingAlgorithm
PRESTO II ProgrammingAlgorithm allows to pro-
gramthe wholearray with a guaranteedmargin, in
a typical time of 3 seconds. Programming with
PRESTOII involvesthe applicationof a sequence
of100
μ
sprogrampulsestoeachbyteuntilacorrect
verify occurs (see Figure 7). During programming
and verify operation, a MARGIN MODE circuit is
automatically activated in order to guaranteethat
each cell is programmedwith enough margin. No
overprogram pulse is applied since the verify in
MARGIN MODE provides necessary margin to
each programmedcell.
ProgramInhibit
Programmingof multipleM27C516sin parallelwith
different data is also easilyaccomplished. Except
for E, all like inputs including G of the parallel
M27C516may be common. ATTL low level pulse
appliedto aM27C516’sPinput,withElowandV
PP
at 12.75V,will programthat M27C516.Ahigh level
E input inhibits the other M27C516s from being
programmed.
ProgramVerify
A verify (read) should be performed on the pro-
grammedbitstodeterminethat theywerecorrectly
programmed. The verify is accomplished with E
and G at V
IL
, P at V
IH
, V
PP
at 12.75V and V
CC
at
6.25V.
8/12
M27C516
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