參數(shù)資料
型號: M27C202-120K6TR
廠商: 意法半導(dǎo)體
英文描述: 2 Mbit 128Kb x16 UV EPROM and OTP EPROM
中文描述: 2兆位存儲器128KB的x16紫外線和OTP存儲器
文件頁數(shù): 13/15頁
文件大?。?/td> 102K
代理商: M27C202-120K6TR
7/15
M27C202
Table 9. Programming Mode DC Characteristics (1)
(TA =25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 10. Programming Mode AC Characteristics (1)
(TA =25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
0
≤ VIN ≤ VIH
±10
A
ICC
Supply Current
50
mA
IPP
Program Current
E= VIL
50
mA
VIL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2
VCC + 0.5
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage TTL
IOH = –400A
2.4
V
VID
A9 Voltage
11.5
12.5
V
Symbol
Alt
Parameter
Test Condi tion
Min
Max
Unit
tAVPL
tAS
Address Valid to Program Low
2
s
tQVPL
tDS
Input Valid to Program Low
2
s
tVPHPL
tVPS
VPP High to Program Low
2
s
tVCHPL
tVCS
VCC High to Program Low
2
s
tELPL
tCES
Chip Enable Low to Program Low
2
s
tPLPH
tPW
Program Pulse Width
95
105
s
tPHQX
tDH
Program High to Input Transition
2
s
tQXGL
tOES
Input Transition to Output Enable Low
2
s
tGLQV
tOE
Output Enable Low to Output Valid
100
ns
tGHQZ
(2)
tDFP
Output Enable High to Output Hi-Z
0
130
ns
tGHAX
tAH
Output Enable High to Address
Transition
0ns
Programming
When delivered (and after each ‘1’s erasure for UV
EPROM), all bits of the M27C202 are in the ’1’
state. Data is introduced by selectively program-
ming ’0’s into the desired bit locations. Although
only ’0’s will be programmed, both ’1’s and ’0’s can
be present in the data word. The only way to
change a ‘0’ to a ‘1’ is by die exposure to ultraviolet
light (UV EPROM). The M27C202 is in the pro-
gramming mode when VPP input is at 12.75V, E is
at VIL and P is pulsed to VIL. The data to be pro-
grammed is applied to 16 bits in parallel, to the
data output pins. The levels required for the ad-
dress and data inputs are TTL. VCC is specified to
be 6.25V
± 0.25V.
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