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參數(shù)資料
| 型號(hào)： | M27C1001-45C6TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Mbit 128Kb x8 UV EPROM and OTP EPROM |
| 中文描述： | 1兆位存儲(chǔ)器的128KB x8紫外線和OTP存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 8/17頁(yè) |
| 文件大小： | 159K |
| 代理商： | M27C1001-45C6TR |
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M27C1001
8/17
PRESTO II Programming Algorithm
PRESTO II Programming Algorithm allows the
whole array to be programmed, with a guaranteed
margin, in a typical time of 13 seconds. Program-
ming with PRESTO II involves in applying a se-
quence of 100μs program pulses to each byte until
a correct verify occurs (see Figure 7). During pro-
gramming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guar-
antee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE provides necessary mar-
gin to each programmed cell.
Program Inhibit
Programming of multiple M27C1001s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27C1001 may be common. A TTL low level
pulse applied to a M27C1001's P input, with E low
and V
PP
at 12.75V, will program that M27C1001.
A high level E input inhibits the other M27C1001s
from being programmed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
and G at V
IL
, P at V
IH
, V
PP
at 12.75V and V
CC
at
6.25V.
Figure 6. Programming and Verify Modes AC Waveforms
tAVPL
VALID
AI00714
A0-A16
Q0-Q7
VPP
VCC
P
G
DATA IN
DATA OUT
E
tQVPL
tVPHPL
tVCHPL
tPHQX
tPLPH
tGLQV
tQXGL
tELPL
tGHQZ
tGHAX
PROGRAM
VERIFY
Figure 7. Programming Flowchart
AI00715C
n = 0
Last
Addr
VERIFY
P = 100
μ
s Pulse
++n
= 25
++ Addr
VCC = 6.25V, VPP = 12.75V
FAIL
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
YES
NO
YES
NO
YES
NO
相關(guān)PDF資料 |
PDF描述 |
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| M27C1001-45C6X | 1 Mbit 128Kb x8 UV EPROM and OTP EPROM |
| M27C1001-45F1TR | 1 Mbit 128Kb x8 UV EPROM and OTP EPROM |
| M27C1001-45F3TR | CAP 3.3PF 50V 10% NP0(C0G) SMD-0805 TR-7-PL SN-NIBAR |
| M27C1001-45F6TR | Ceramic Chip Capacitors / Standard C0G; Capacitance [nom]: 36pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Tin Plated Nickel Barrier; Body Dimensions: 0.079" x 0.049"; Container: Bulk; Features: Unmarked |
| M27C1001-60B1TR | 1 Mbit 128Kb x8 UV EPROM and OTP EPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M27C1001-45C6X | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:1 Mbit 128Kb x8 UV EPROM and OTP EPROM |
| M27C1001-45CTR | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:1 Mbit (128 Kbit x 8) UV EPROM and OTP EPROM |
| M27C1001-45F1 | 制造商:STMicroelectronics 功能描述:IC EPROM CMOS 1MB 27C1001 DIP32 制造商:STMicroelectronics 功能描述:IC EPROM CMOS 1MB 27C1001 TUBE12 |
| M27C1001-45F1 | 制造商:STMicroelectronics 功能描述:IC EPROM CMOS 1MB 27C1001 DIP32 |
| M27C1001-45F1TR | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:1 Mbit 128Kb x8 UV EPROM and OTP EPROM |
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