參數(shù)資料
          型號: M24C64-RDW3
          廠商: 意法半導(dǎo)體
          元件分類: EEPROM
          英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
          中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
          文件頁數(shù): 18/26頁
          文件大小: 394K
          代理商: M24C64-RDW3
          M24C64, M24C32
          18/26
          Table 16. AC Characteristics (M24Cxx-6, M24Cxx-W6 and M24Cxx-W3)
          Test conditions specified in
          Table 11.
          and
          Table 8.
          or
          Table 9.
          Note: 1. For a reSTART condition, or following a Write cycle.
          2. Sampled only, not 100% tested.
          3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
          4. The Write Time of 5 ms only applies to devices bearing the process letter “B” in the package marking (on the top side of the pack-
          age), otherwise (for devices bearing the process letter “N”) the Write Time is 10 ms. For further details, please contact your nearest
          ST sales office, and ask for a copy of the Product Change Notice PCEE0036.
          Table 17. AC Characteristics (M24Cxx-R)
          Note: 1. For a reSTART condition, or following a Write cycle.
          2. Sampled only, not 100% tested.
          3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
          Symbol
          Alt.
          Parameter
          Min.
          Max.
          Unit
          f
          C
          f
          SCL
          Clock Frequency
          400
          kHz
          t
          CHCL
          t
          HIGH
          Clock Pulse Width High
          600
          ns
          t
          CLCH
          t
          LOW
          Clock Pulse Width Low
          1300
          ns
          t
          DL1DL2 2
          t
          F
          SDA Fall Time
          20
          300
          ns
          t
          DXCX
          t
          SU:DAT
          Data In Set Up Time
          100
          ns
          t
          CLDX
          t
          HD:DAT
          Data In Hold Time
          0
          ns
          t
          CLQX
          t
          DH
          Data Out Hold Time
          200
          ns
          t
          CLQV 3
          t
          AA
          Clock Low to Next Data Valid (Access Time)
          200
          900
          ns
          t
          CHDX 1
          t
          SU:STA
          Start Condition Set Up Time
          600
          ns
          t
          DLCL
          t
          HD:STA
          Start Condition Hold Time
          600
          ns
          t
          CHDH
          t
          SU:STO
          Stop Condition Set Up Time
          600
          ns
          t
          DHDL
          t
          BUF
          Time between Stop Condition and Next Start Condition
          1300
          ns
          t
          W
          t
          WR
          Write Time
          5 or
          4
          10
          ms
          Test conditions specified in
          Table 11.
          and
          Table 10.
          Symbol
          Alt.
          Parameter
          Min.
          Max.
          Unit
          f
          C
          f
          SCL
          Clock Frequency
          400
          kHz
          t
          CHCL
          t
          HIGH
          Clock Pulse Width High
          600
          ns
          t
          CLCH
          t
          LOW
          Clock Pulse Width Low
          1300
          ns
          t
          DL1DL2 2
          t
          F
          SDA Fall Time
          20
          300
          ns
          t
          DXCX
          t
          SU:DAT
          Data In Set Up Time
          100
          ns
          t
          CLDX
          t
          HD:DAT
          Data In Hold Time
          0
          ns
          t
          CLQX
          t
          DH
          Data Out Hold Time
          200
          ns
          t
          CLQV 3
          t
          AA
          Clock Low to Next Data Valid (Access Time)
          200
          900
          ns
          t
          CHDX 1
          t
          SU:STA
          Start Condition Set Up Time
          600
          ns
          t
          DLCL
          t
          HD:STA
          Start Condition Hold Time
          600
          ns
          t
          CHDH
          t
          SU:STO
          Stop Condition Set Up Time
          600
          ns
          t
          DHDL
          t
          BUF
          Time between Stop Condition and Next Start Condition
          1300
          ns
          t
          W
          t
          WR
          Write Time
          10
          ms
          相關(guān)PDF資料
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          M24C64-RDW3P The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
          M24C64-RDW3T The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
          M24C64-RDW3TP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
          M24C64-RDW6 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
          M24C64-RDW6P The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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