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M24512
REVISION HISTORY
Table 21. Document Revision History
Date
Revision
Description of Revision
29-Jan-2001
1.1
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
LGA8 and SO8(wide) packages added
References to PSDIP8 changed to PDIP8, and Package Mechanical data updated
10-Apr-2001
1.2
LGA8 Package Mechanical data and illustration updated
SO16 package removed
16-Jul-2001
1.3
LGA8 Package given the designator “LA”
02-Oct-2001
1.4
LGA8 Package mechanical data updated
13-Dec-2001
1.5
Document becomes Preliminary Data
Test conditions for ILI, ILO, ZL and ZH made more precise
VIL and VIH values unified. tNS value changed
12-Jun-2001
1.6
Document promoted to Full Datasheet
22-Oct-2003
2.0
Table of contents, and Pb-free options added. Minor wording changes in Summary 
Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations. 
V
IL
(min) improved to –0.45V.
02-Sep-2004
3.0
LGA8 package is Not for New Design. 5V and -S supply ranges, and Device Grade 5 
removed. Absolute Maximum Ratings for V
IO
(min) and V
CC
(min) changed. Soldering 
temperature information clarified for RoHS compliant devices. Device grade information 
clarified. AEC-Q100-002 compliance. V
IL
 specification unified for SDA, SCL and WC
22-Feb-2005
4.0
INITIAL DELIVERY STATE
 is FFh (not necessarily the same as Erased). 
LGA package removed, TSSOP8 and SO8N packages added (see 
PACKAGE 
MECHANICAL
 section and 
Table 20., Ordering Information Scheme
).
Voltage range R (1.8V to 5.5V) also offered. Minor wording changes.
Z
L
 Test Conditions modified in 
Table 11., Input Parameters
 and Note 
3.
 added. 
I
CC
 and I
CC1
 values for V
CC
 = 5.5V added to 
Table 12., DC Characteristics (M24512 – W)
. 
Note added to 
Table 12., DC Characteristics (M24512 – W)
. 
Power On Reset
 paragraph specified.
t
W
 max value modified in 
Table 14., AC Characteristics (M24512 – W)
 and note 4 added. 
Plating technology changed in 
Table 20., Ordering Information Scheme
.
Resistance and capacitance renamed in 
Figure 4., Maximum R
P
 Value versus Bus 
Parasitic Capacitance (C) for an I
2
C Bus
.