參數(shù)資料
型號(hào): M21L216128A-15T
廠商: Electronic Theatre Controls, Inc.
英文描述: 128 K x 16 SRAM HIGH SPEED CMOS SRAM
中文描述: 128畝× 16 SRAM的高速CMOS的SRAM
文件頁(yè)數(shù): 4/14頁(yè)
文件大?。?/td> 168K
代理商: M21L216128A-15T
(607
M21L216128A
Elite Semiconduture Memory Technology Inc
Publication Date
:
Sep. 2000
Revision
:
1.0
4/14
AC ELECTRICAL CHARACTERISTICS
(Note 5)(All Temperature Ranges; V
CC
=3.3V
±
0.3V)
-10
-12
-15
Notes
DESCRIPTION
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Read Cycle
Read Cycle Time
t
RC
10
12
15
ns
Access access time
t
AA
10
12
15
ns
Chip Enable access time
t
ACE
10
12
15
ns
Output hold from address change
t
OH
3
4
4
ns
Chip Enable to output in Low-Z
t
CLZ
3
4
4
ns
4,7
Chip disable to output in High-Z
t
CHZ
5
6
7
ns
4,6,7
Output Enable access time
t
OE
5
6
7
ns
Output Enable to output in Low-Z
t
OLZ
0
0
0
ns
Output Disable to output in High-Z
t
OHZ
5
6
7
ns
4,6
Byte Enable access time
t
BE
6
7
8
ns
Byte Enable to output in Low-Z
t
BLZ
0
0
0
ns
4,7
Byte disable to output in High-Z
t
BHZ
5
6
7
ns
4,6,7
Write Cycle
Write cycle time
t
WC
10
12
15
ns
Chip Enable to end of write
t
CW
8
8
9
ns
Address valid to end of write, with
OE
HIGH
t
AW
8
8
9
ns
Address setup time
t
AS
0
0
0
ns
Address hold from end of write
t
WR
0
0
0
ns
Write pulse width
t
WP2
10
10
11
ns
Write pulse width, with
OE
HIGH
t
WP1
8
8
9
ns
Data setup time
t
DW
5
6
7
ns
Data hold time
t
DH
0
0
0
ns
Write disable to output in Low-Z
t
OW
3
4
5
ns
4,7
Byte Enable to output in High-Z
t
WHZ
5
6
7
ns
4,6,7
Byte Enable to end of write
t
BW
8
8
9
ns
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