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| 型號(hào)： | M2006-12I-672.1600 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁(yè)數(shù)： | 4/8頁(yè) |
| 文件大?。?/td> | 374K |
| 代理商： | M2006-12I-672.1600 |
M2006-12 Datasheet Rev 1.0
4 of 8
Revised 13Jul2004
I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0
M2006-12
VCSO BASED FEC CLOCK PLL
Prod uct Data Sh eet
The PLL
The PLL uses a phase detector and configurable
dividers to synchronize the output of the VCSO with
selected reference clock.
The “Mfin Divider” and “Mfec Divider” divide the VCSO
frequency, feeding the result into the phase detector.
The selected input reference clock is divided by the
“Rfec Divider”. The result is fed into the other input of
the phase detector.
The phase detector compares its two inputs. It then
outputs pulses to the loop filter as needed to increase or
decrease the VCSO frequency and thereby match and
lock the divider output’s frequency and phase to those
of the input reference clock.
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
See also “Maintaining PLL Lock:” on pg. 4.
Relationship Among Frequencies and Dividers
The VCSO center frequency must be specified at time
of order. The relationship between the VCSO (Fvcso)
frequency, the Mfin divider, the Mfec divider, the Rfec
divider, and the input reference frequency (Fin) is:
As an example, for the M2006-12-622.0800, the non-FEC
and inverse-FEC PLL ratios in Table 4 enable use with
these corresponding input reference frequencies:
Maintaining PLL Lock:
The narrow tuning range of the VCSO requires that the
input reference frequency must remain suitable for the
current look-up table selection. For example, when
switching between “Inverse FEC ratio” and “Non-FEC
input reference frequency must change accordingly in
order for the PLL to lock.
An out-of-lock condition due to an inappropriate
configuration will typically result in the VCSO
operating at its lower or upper frequency rail,
which is approximately 200ppm above or below
the nominal VCSO center frequency.
See also “Hitless Switching (HS)” (next) for an
additional issue with regard to phase locking.
Hitless Switching (HS)
The M2006-12 includes a proprietary Hitless Switching
(HS) feature that prevents excessive phase transients
of the output clocks upon input reference
rearrangement. Upon the occurance of an input
reference phase change, or phase transient, PLL
bandwidth is lowered by the HS function. This limits the
rate of phase change in the output clocks. With proper
configuration of the external loop filter, the output clocks
will comply with MTIE (maximum time interval error)
specifications for GR-253 (SONET) and ITU G.813
(SDH) during input reference clock changes.
The HS function uses a phase error detector at the
phase detector to detect a clock phase change. During
normal operation with a stable reference clock, the PLL
will be frequency locked and phase locked, resulting in
very little error at the phase detector (<1 ns). Upon the
selection of a new input reference clock at a different
clock phase, a phase error will occur at the phase
detector. The HS function is triggered with a phase error
greater than 4 ns, upon which a narrow PLL bandwidth
is applied. When the PLL locks to within 2 ns error at the
phase detector, wide bandwidth (normal) operation is
resumed.
The HS function is not suitable for situations in which an
unstable reference is used. Under normal conditions
the reference clock jitter should not induce phase jitter
at the phase detector beyond 2 ns. (This includes when
subjecting the system to jitter tolerance compliance
testing.) Because of this, the M2006-12 is not
recommended for use with some Stratum DPLL clock
sources, or with unstable recovered network clocks
intended for loop timing configuration. It is also not
recommended for complex FEC ratios where the phase
detector is operated at less 1 MHz. For these
applications the M2006-02 is suggested. The M2006-02
is identical to the M2006-12 except that it does not
include the HS function (nor the APC pin and phase
build-out function, which are discussed in the following
section).
M2006-12-622.0800
VCSO Clock
Frequency (MHz)
FEC Ratio
=
Base Input Ref.
Frequency (MHz) 1
Note 1: Input reference clock (“Fin”) can be the base frequency
622.08
1
/
1
622.0800
238
/ 255
666.5143
237
/ 255
669.3266
236
/ 255
672.1627
Table 6: Example FEC PLL Rations and Input Reference Frequencies
Fvcso
Fin
Mfin
×
Mfec
Rfec
--------------
×
=
÷
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