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參數(shù)資料
| 型號(hào)： | M2006-12I-669.1281 |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大小： | 374K |
| 代理商： | M2006-12I-669.1281 |
M2006-12 Datasheet Rev 1.0
2 of 8
Revised 13Jul2004
I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0
M2006-12
VCSO BASED FEC CLOCK PLL
Prod uct Data Sh eet
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number
Name
I/O
Configuration
Description
1, 2, 3, 10, 14, 26
GND
Ground
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections. See Figure 4.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12, 13
FOUT1, nFOUT1
Output
No internal terminator
Clock output pairs. Differential LVPECL.
15, 16
FOUT0, nFOUT0
17
18
P1_SEL
P0_SEL
Input
Internal pull-down resistor1
P Divider controls. LVCMOS/LVTTL.
20
21
nDIF_REF1
Input
Internal pull-UP resistor1
Reference clock input pair 1.
Differential LVPECL or LVDS.
DIF_REF1
Internal pull-down resistor1
22
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
23
24
nDIF_REF0
Input
Internal pull-UP resistor1
Reference clock input pair 0.
Differential LVPECL or LVDS.
DIF_REF0
Internal pull-down resistor1
25
APC
Input
Internal pull-down resistor1
Automatic Phase Compensation (phase
build-out). LVCMOS/LVTTL:
Logic 1 - Device absorbs input phase transients.
Logic 0 - Device doesn’t absorb transients.
27
28
FIN_SEL1
FIN_SEL0
Input
Internal pull-down resistor1
I
nput clock frequency selection. LVCMOS/LVTTL.
29
30
31
32
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
Input
Internal pull-UP resistor1
FEC PLL divider ratio selection. LVCMOS/ LVTTL.
34, 35, 36
DNC
Do Not Connect.
Internal nodes. Connection to these pins can
cause erratic device operation.
Table 2: Pin Descriptions
M2006-12
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
External
Loop Filter
Components
nFOUT0
FEC_SEL3:0
P0_SEL
FIN_SEL1:0
MUX
0
REF_SEL
APC
DIF_REF1
nDIF_REF1
DIF_REF0
nDIF_REF0
1
nFOUT1
P1_SEL
2
Divider LUT
4
LUT
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