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| 型號(hào)： | M2006-12I-627.3296 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大小： | 374K |
| 代理商： | M2006-12I-627.3296 |
M2006-12 Datasheet Rev 1.0
5 of 8
Revised 13Jul2004
Integr ated Circuit Systems , Inc. ● Netw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (5 08) 85 2-54 00
M2006-12
VCSO BASED FEC CLOCK PLL
Prod uct Data Sh eet
Automatic Phase Compensation (APC) Pin
The M2006-12 also includes a phase build-out function
that can be selectively enabled by asserting the APC
input (pin 25) to logic 1. The phase build-out function
works in conjunction with the HS function. When the
APC pin is asserted, the phase build-out function
enables the PLL to absorb most of the phase change of
the input clock which reduces re-lock time and the
generation of wander. (Wander is created in this case
by the generation of extra output clock cycles.)
When the APC pin is asserted, the phase build-out
function is triggered by same >4 ns phase transient (at
the phase detector) that triggers the HS function. Once
triggered, a new VCSO clock edge is selected for the
phase comparator feedback input. (The clock edge
selected is the one closest in phase to the new input
clock phase.) The residual phase detector phase error
following reselection is approximately 3-to-4 ns. The
narrow bandwidth selected by the HS function
minimizes VCSO drifting and switch transients during
the process.
It is recommended that the APC pin remain low when
the phase detector frequency is less than 4 MHz.
Otherwise, the M2006-12 may have difficulty locking to
reference upon power-up.
Outputs
The M2006-12 provides a total of two differential
LVPECL output pairs: FOUT1 and FOUT0. Because each
output pair has its own P divider, the FOUT1 pair and the
FOUT0
can output the two different frequencies at the
same time. For example, FOUT1 can output 155.52MHz
while FOUT0 outputs 622.08MHz.
Any unused output should be left unconnected
(floating) in the system application. This will
minimize output switching current and therefore
minimize noise modulation of the VCSO.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M2006-12 requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 4).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
Figure 4: External Loop Filter
PLL bandwidth is affected by the “Mfec” value and the
“Mfin” value, as well as the VCSO frequency.
The various “Non-FEC ratio” settings can be used to
actively change PLL loop bandwidth in a given
application. See “FEC PLL Ratio Dividers Look-up
Consult factory for external loop filter component values.
PLL Simulator Tool Available
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter
Rating
Unit
V
I
Inputs
-0.5 to V
CC +0.5
V
O
Outputs
-0.5 to V
CC +0.5
V
CC
Power Supply Voltage
4.6
V
T
S
Storage Temperature
-45 to +100
oC
Table 7: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
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