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| 型號(hào)： | M2006-11-622.0800LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁(yè)數(shù)： | 1/14頁(yè) |
| 文件大?。?/td> | 433K |
| 代理商： | M2006-11-622.0800LF |
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M2006-11 Datasheet Rev 0.1
Revised 29Apr2003
Integ r ated Circuit Systems , Inc. ● Comm unications Modules ● www.icst.com ● tel (508) 852-5400
M2006-11
VCSO BASED FREQUENCY TRANSLATOR WITH APS
Product Data Sheet
GENERAL DESCRIPTION
The M2006-11 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
It features serially programmable
configuration of PLL frequency
translation ratios, including FEC
and inverse FEC. The device is
similar to the M2006-04 (compatible pins and functions)
but additionally provides automatic protection switching
(APS) and automatic phase compensation functions.
FEATURES
◆ Integrated SAW (surface acoustic wave) delay line
◆ VCSO frequency from 300 to 700MHz
(Specify center frequency at time of order)
◆ Low phase jitter 0.5ps rms, typical (12kHz to 20MHz or
50kHz to 80MHz)
◆ Similar to the M2006-04 (and pin-compatible), except
adds APS (automatic protection switching) and APC
◆ APS narrows loop bandwidth when switching input
references to maintain GR-253 MTIE and TDEV
compliance
◆ APS is triggered by a > 4 ns clock phase change at
input
◆ Automatic Phase Compensation (APC) function
enables absorption of the input phase change.
◆ Narrow Bandwidth (NBW) control pin provides manual
PLL control (set high for narrow bandwidth)
◆ Clock Add/Drop feature enables data FIFO centering
◆ Universal differential reference inputs support LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
◆ Power-up default x32 multiplication ratio suitable for
many optical networking applications
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example Input / Output Frequency Combinations
Input Clock
(MHz)
VCSO
Freq1 (MHz)
Note 1: Specify VCSO center frequency at time of order
Output
Freq (MHz)
Application
19.44
622.08
OC-12/48
155.52
19.53125
625.00
156.25
Gigabit Ethernet
Using Power-up PLL Ratio
M2006-11 VCSO Based Frequency Translator with APS
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| M2006-12 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION |
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| M2006-12A-622.0800 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
| M2006-12A-625.0000 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
| M2006-12A-669.3266 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
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