2-62 Revision 13 Differential I/O Characteristics Physical Implementation Configuration of the I/O " />
參數(shù)資料
型號： M1AGLE3000V5-FGG896
廠商： Microsemi SoC
文件頁數(shù)： 141/166頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 3M 896-FBGA
標準包裝： 27
系列： IGLOOe
邏輯元件/單元數(shù)： 75264
RAM 位總計： 516096
輸入/輸出數(shù)： 620
門數(shù)： 3000000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 896-BGA
供應商設備封裝： 896-FBGA（31x31）
IGLOOe DC and Switching Characteristics
2-62
Revision 13
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by the Microsemi Designer software
when the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for bidirectional
I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-23. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, IGLOOe also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Figure 2-23 LVDS Circuit Diagram and Board-Level Implementation
140
100
Z0 = 50
165
165
+
–
P
N
P
N
INBUF_LVDS
OUTBUF_LVDS
FPGA
Bourns Part Number: CAT16-LV4F12
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