Revision 23 2-49 Table 2-65 Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applica" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� M1AGL250V2-VQ100
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 213/250闋�
鏂囦欢澶�?銆�?/td> 0K
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RAM 浣嶇附瑷�(j矛)锛� 36864
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IGLOO Low Power Flash FPGAs
Revision 23
2-49
Table 2-65 Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
Applicable to Standard I/O Banks
3.3 V LVCMOS Wide Range
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL2 IIH3
Drive
Strength
Equivalent
Software
Default Drive
Strength
Option1
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VA
A
Max.
mA4
Max.
mA4
A5 A5
100 A
2 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100 100
25
27
10
100 A
4 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100 100
25
27
10
100 A
6 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100 100
51
54
10
100 A
8 mA
鈥�0.3
0.8
2
3.6
0.2
VDD 鈥� 0.2 100 100
51
54
10
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤 100 A. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 100掳C junction temperature and maximum voltage.
5. Currents are measured at 85掳C junction temperature.
6. Software default selection highlighted in gray.
Table 2-66 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
03.3
1.4
5
Note: *Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points.
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