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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | M1AGL1000V5-FG256 |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 246/250闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 1KB FLASH 1M 256-FBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | IGLOO |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 24576 |
| RAM 浣嶇附瑷堬細 | 147456 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 177 |
| 闁€鏁�(sh霉)锛� | 1000000 |
| 闆绘簮闆诲锛� | 1.425 V ~ 1.575 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 256-LBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 256-FPBGA锛�17x17锛� |
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IGLOO Low Power Flash FPGAs
Revision 23
2-79
1.2 V DC Core Voltage
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Microsemi Designer software when
the user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, IGLOO also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
Table 2-145 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
1.55
2.91
0.25
0.86
1.10
2.95
2.29
3.25
3.93
8.74
8.08
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Table 2-146 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Speed Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
1.55
2.53
0.25
0.85
1.10
2.57
1.98
2.93
3.64
8.35
7.76
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Figure 2-13 LVDS Circuit Diagram and Board-Level Implementation
140
100
Z0 = 50
165
165
+
鈥�
P
N
P
N
INBUF_LVDS
OUTBUF_LVDS
FPGA
Bourns Part Number: CAT16-LV4F12
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| AGL1000V5-FG256 | IC FPGA 1KB FLASH 1M 256FBGA |
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| ABC44DRYN-S734 | CONN EDGECARD 88POS DIP .100 SLD |
| M7A3P1000-FGG144 | IC FPGA 1KB FLASH 1M 144-FBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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