Revision 4 2-177 Table 2-99 Short Current Event Duration before Failure Temperature Time before Failur" />
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鍨嬭櫉锛� M1AFS250-1QNG180
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 105/334闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 2MB FLASH 250K 180-QFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 184
绯诲垪锛� Fusion®
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 65
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 180-WFQFN
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 180-QFN锛�10x10锛�
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Fusion Family of Mixed Signal FPGAs
Revision 4
2-177
Table 2-99 Short Current Event Duration before Failure
Temperature
Time before Failure
鈥�40掳C
>20 years
0掳C
>20 years
25掳C
>20 years
70掳C
5 years
85掳C
2 years
100掳C
6 months
Table 2-100 Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
240 mV
2.5 V LVCMOS (Schmitt trigger mode)
140 mV
1.8 V LVCMOS (Schmitt trigger mode)
80 mV
1.5 V LVCMOS (Schmitt trigger mode)
60 mV
Table 2-101 I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
Input Rise/Fall Time (min.)
Input Rise/Fall Time (max.)
Reliability
LVTTL/LVCMOS (Schmitt trigger
disabled)
No requirement
10 ns*
20 years (100掳C)
LVTTL/LVCMOS (Schmitt trigger
enabled)
No requirement
No requirement, but input
noise voltage cannot exceed
Schmitt hysteresis
20 years (100掳C)
HSTL/SSTL/GTL
No requirement
10 ns*
10 years (100掳C)
LVDS/BLVDS/M-LVDS/LVPECL
No requirement
10 ns*
10 years (100掳C)
Note: *The maximum input rise/fall time is related only to the noise induced into the input buffer trace. If the noise is
low, the rise time and fall time of input buffers, when Schmitt trigger is disabled, can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise.
Microsemi recommends signal integrity evaluation/characterization of the system to ensure there is no excessive
noise coupling into input signals.
鐩搁棞(gu膩n)PDF璩囨枡
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